Pushing the level of abstraction of digital system design: A survey on how to program fpgas

ED Sozzo, D Conficconi, A Zeni, M Salaris… - ACM Computing …, 2022 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations

A Izraelevitz, J Koenig, P Li, R Lin… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
Enabled by modern languages and retargetable compilers, software development is in a
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …

Convolution engine: balancing efficiency & flexibility in specialized computing

W Qadeer, R Hameed, O Shacham… - Proceedings of the 40th …, 2013 - dl.acm.org
This paper focuses on the trade-off between flexibility and efficiency in specialized
computing. We observe that specialized units achieve most of their efficiency gains by tuning …

[PDF][PDF] Darkroom: compiling high-level image processing code into hardware pipelines.

J Hegarty, JS Brunhaver, Z DeVito, J Ragan-Kelley… - ACM Trans. Graph., 2014 - Citeseer
Specialized image signal processors (ISPs) exploit the structure of image processing
pipelines to minimize memory bandwidth using the architectural pattern of line-buffering …

PyMTL: A unified framework for vertically integrated computer architecture research

D Lockhart, G Zibrat, C Batten - 2014 47th Annual IEEE/ACM …, 2014 - ieeexplore.ieee.org
Technology trends prompting architects to consider greater heterogeneity and hardware
specialization have exposed an increasing need for vertically integrated research …

A modular digital VLSI flow for high-productivity SoC design

B Khailany, E Khmer, R Venkatesan… - Proceedings of the 55th …, 2018 - dl.acm.org
A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow
includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and …

Performance improvement and hardware implementation of open flow switch using FPGA

A Yazdinejad, A Bohlooli… - 2019 5th Conference on …, 2019 - ieeexplore.ieee.org
The architecture of current networks is static and nonprogrammable. In Software-Defined
Networking (SDN) it is possible to have programmability and innovation within the network …

Strober: Fast and accurate sample-based energy simulation for arbitrary RTL

D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer… - ACM SIGARCH …, 2016 - dl.acm.org
This paper presents a sample-based energy simulation methodology that enables fast and
accurate estimations of performance and average power for arbitrary RTL designs. Our …

Low power programmable image processor

R Hameed, W Qadeer, C Kozyrakis… - US Patent …, 2016 - Google Patents
BACKGROUND In recent times, there has been a dramatic shift in con Sumer photography.
Once dominated by dedicated cameras and photography equipment, a majority of pictures …

[PDF][PDF] Evaluation of RISC-V RTL with FPGA-accelerated simulation

D Kim, C Celio, D Biancolin, J Bachrach… - First Workshop on …, 2017 - carrv.github.io
This paper presents a fast and accurate simulation methodology for performance, power,
and energy evaluation in the hardware/software co-design flow. Cycle-level …