A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications

L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin… - ACM Computing …, 2019 - dl.acm.org
As general-purpose processors have hit the power wall and chip fabrication cost escalates
alarmingly, coarse-grained reconfigurable architectures (CGRAs) are attracting increasing …

A case for intelligent RAM

D Patterson, T Anderson, N Cardwell, R Fromm… - IEEE micro, 1997 - ieeexplore.ieee.org
Two trends call into question the current practice of fabricating microprocessors and DRAMs
as different chips on different fabrication lines. The gap between processor and DRAM …

Hardnet: A low memory traffic network

P Chao, CY Kao, YS Ruan… - Proceedings of the …, 2019 - openaccess.thecvf.com
State-of-the-art neural network architectures such as ResNet, MobileNet, and DenseNet
have achieved outstanding accuracy over low MACs and small model size counterparts …

Photon: A fast query engine for lakehouse systems

A Behm, S Palkar, U Agarwal, T Armstrong… - Proceedings of the …, 2022 - dl.acm.org
Many organizations are shifting to a data management paradigm called the" Lakehouse,"
which implements the functionality of structured data warehouses on top of unstructured …

Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures

YS Shao, B Reagen, GY Wei, D Brooks - ACM SIGARCH Computer …, 2014 - dl.acm.org
Hardware specialization, in the form of accelerators that provide custom datapath and
control for specific algorithms and applications, promises impressive performance and …

[图书][B] Memory systems: cache, DRAM, disk

B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

[图书][B] Parallel computer architecture: a hardware/software approach

D Culler, JP Singh, A Gupta - 1999 - books.google.com
The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …

Memory coherence in shared virtual memory systems

K Li, P Hudak - ACM Transactions on Computer Systems (TOCS), 1989 - dl.acm.org
The memory coherence problem in designing and implementing a shared virtual memory on
loosely coupled multiprocessors is studied in depth. Two classes of algorithms, centralized …

Co-designing accelerators and SoC interfaces using gem5-Aladdin

YS Shao, SL Xi, V Srinivasan, GY Wei… - 2016 49th Annual …, 2016 - ieeexplore.ieee.org
Increasing demand for power-efficient, high-performance computing has spurred a growing
number and diversity of hardware accelerators in mobile and server Systems on Chip …

Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

A Jog, AK Mishra, C Xu, Y Xie, V Narayanan… - Proceedings of the 49th …, 2012 - dl.acm.org
High density, low leakage and non-volatility are the attractive features of Spin-Transfer-
Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a …