A survey of architectural techniques for improving cache power efficiency

S Mittal - Sustainable Computing: Informatics and Systems, 2014 - Elsevier
Modern processors are using increasingly larger sized on-chip caches. Also, with each
CMOS technology generation, there has been a significant increase in their leakage energy …

Drowsy caches: simple techniques for reducing leakage power

K Flautner, NS Kim, S Martin, D Blaauw… - ACM SIGARCH …, 2002 - dl.acm.org
On-chip caches represent a sizable fraction of the total power consumption of
microprocessors. Although large caches can significantly improve performance, they have …

[图书][B] The VLSI handbook

WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …

[PDF][PDF] Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects

Y Zhang, D Parikh, K Sankaranarayanan, K Skadron… - 2003 - cs.virginia.edu
This report introduces HotLeakage, an architectural model for subthreshold and gate
leakage that we have developed here at the University of Virginia. The most important …

Circuit and microarchitectural techniques for reducing cache leakage power

NS Kim, K Flautner, D Blaauw… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
On-chip caches represent a sizable fraction of the total power consumption of
microprocessors. As feature sizes shrink, the dominant component of this power …

Adaptive mode control: A static-power-efficient cache design

H Zhou, MC Toburen, E Rotenberg… - ACM Transactions on …, 2003 - dl.acm.org
Lower threshold voltages in deep submicron technologies cause more leakage current,
increasing static power dissipation. This trend, combined with the trend of larger/more cache …

Drowsy instruction caches. leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

NS Kim, K Flautner, D Blaauw… - 35th Annual IEEE/ACM …, 2002 - ieeexplore.ieee.org
On-chip caches represent a sizeable fraction of the total power consumption of
microprocessors. Although large caches can significantly improve performance, they have …

Design techniques and architectures for low-leakage SRAMs

A Calimera, A Macii, E Macii… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
In high performance Systems-on-Chip, leakage power consumption has become
comparable to the dynamic component, and its relevance increases as technology scales …

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

K Osada, Y Saitoh, E Ibe… - IEEE Journal of Solid …, 2003 - ieeexplore.ieee.org
Tunnel-leakage currents become the dominant form of leakage as MOS technology
advances. An electric-field-relaxation scheme that suppresses these currents is described …

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

K Nii, Y Tsukamoto, T Yoshizawa… - IEEE Journal of Solid …, 2004 - ieeexplore.ieee.org
In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total
standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that …