A survey of research and practices of network-on-chip
T Bjerregaard, S Mahadevan - ACM Computing Surveys (CSUR), 2006 - dl.acm.org
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …
[引用][C] Texturing & Modeling, A procedural Approach
DS Ebert - 2002 - books.google.com
The third edition of this classic tutorial and reference on procedural texturing and modeling
is thoroughly updated to meet the needs of today's 3D graphics professionals and students …
is thoroughly updated to meet the needs of today's 3D graphics professionals and students …
StreamIt: A language for streaming applications
W Thies, M Karczmarek, S Amarasinghe - … , CC 2002 Held as Part of the …, 2002 - Springer
We characterize high-performance streaming applications as a new and distinct domain of
programs that is becoming increasingly important. The StreamIt language provides novel …
programs that is becoming increasingly important. The StreamIt language provides novel …
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in
which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of …
which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of …
A survey on coarse-grained reconfigurable architectures from a performance perspective
With the end of both Dennard's scaling and Moore's law, computer users and researchers
are aggressively exploring alternative forms of computing in order to continue the …
are aggressively exploring alternative forms of computing in order to continue the …
Dynamic warp formation and scheduling for efficient GPU control flow
WWL Fung, I Sham, G Yuan… - 40th Annual IEEE/ACM …, 2007 - ieeexplore.ieee.org
Recent advances in graphics processing units (GPUs) have resulted in massively parallel
hardware that is easily programmable and widely available in commodity desktop computer …
hardware that is easily programmable and widely available in commodity desktop computer …
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
K Sankaralingam, R Nagarajan, H Liu, C Kim… - Proceedings of the 30th …, 2003 - dl.acm.org
This paper describes the polymorphous TRIPS architecture which can be configured for
different granularities and types of parallelism. TRIPS contains mechanisms that enable the …
different granularities and types of parallelism. TRIPS contains mechanisms that enable the …
Scaling to the End of Silicon with EDGE Architectures
Microprocessor designs are on the verge of a post-RISC era in which companies must
introduce new ISAs to address the challenges that modern CMOS technologies pose while …
introduce new ISAs to address the challenges that modern CMOS technologies pose while …
Smart memories: A modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly
focused to achieve high performance and high efficiency, yet also target the high volumes …
focused to achieve high performance and high efficiency, yet also target the high volumes …
MIMD Programs Execution Support on SIMD Machines: A Holistic Survey
D Mustafa, R Alkhasawneh, F Obeidat… - IEEE Access, 2024 - ieeexplore.ieee.org
The Single Instruction Multiple Data (SIMD) architecture, supported by various high-
performance computing platforms, efficiently utilizes data-level parallelism. The SIMD model …
performance computing platforms, efficiently utilizes data-level parallelism. The SIMD model …