Chip multi-threaded (CMT) processors provide support for many simultaneous hardware
threads of execution in various ways, including simultaneous multithreading (SMT) and chip …

The vector-thread (VT) architectural paradigm unifies the vectorand multithreaded compute
models. The VT abstraction providesthe programmer with a control processor and a vector of …

We present a taxonomy and modular implementation approach for data-parallel
accelerators, including the MIMD, vector-SIMD, subword-SIMD, SIMT, and vector-thread (VT) …

A data processing apparatus has a cache and a translation look aside buffer (TLB). A way
table is provided for identifying which of a plurality of cache ways stores require data. Each …

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with
fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters …

Having hit power limitations to even more aggressive out-of-order execution in processor
cores, many architects in the past decade have turned to single-instruction-multiple-data …

This paper describes the system architecture of the Cray BlackWidow scalable vector
multiprocessor. The BlackWidow system is a distributed shared memory (DSM) architecture …

This work-in-progress document outlines the fourth version of the Hwacha vector-fetch
architecture. Inspired by traditional vector machines from the 1970s and 1980s such as the …

We describe a tiled architecture that can fluidly transition between manycore (MIMD) and
vector (SIMD) execution. The hardware provides a software-defined vector programming …

As we approach the end of conventional technology scaling, computer architects are forced
to incorporate specialized and heterogeneous accelerators into general-purpose processors …