S Wairya, RK Nagaria, S Tiwari - International Journal of VLSI …, 2012 - academia.edu
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A …
We present a high-speed, energy-efficient Convolutional Neural Network (CNN) architecture utilising the capabilities of a unique class of devices known as analog Focal Plane Sensor …
S Janwadkar, S Das - 2018 3rd International Conference for …, 2018 - ieeexplore.ieee.org
Modern VLSI techniques focus greatly on High Speed Propagation and Low Power Consumption. In this research paper, we present a hybrid 1-bit full adder design which …
The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a …
N Yadav, S Khandelwal… - … Conference on Control …, 2013 - ieeexplore.ieee.org
The conventional single-gate MOSFETs faces great challenges in scaling down of devices due to the severe short-channel effects that reason an exponential gain in the leakage …
Integrated circuit has been widely used in different applications. The design and development of CMOS transistor provides various advantages such as low power …
Reversible logic has gained importance in the present development of low-power and high- speed digital systems in nanotechnology. In this manuscript, we have introduced and …
S Yadav, Y Bansal, B Joseph… - 2022 IEEE Delhi Section …, 2022 - ieeexplore.ieee.org
This paper proposes a dual-Vt 7T SRAM with a distinct read leakage path. The proposed dual-Vt 7T SRAM features low leakage current because of its single-ended operation which …
Efficiency of adiabatic logic circuits is determined by the adiabatic and non‐adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these …