[HTML][HTML] GDI based full adders for energy efficient arithmetic applications

M Shoba, R Nakkeeran - … Science and Technology, an International Journal, 2016 - Elsevier
Addition is a vital arithmetic operation and acts as a building block for synthesizing all other
operations. A high-performance adder is one of the key components in the design of …

[PDF][PDF] Comparative performance analysis of XORXNOR function based high-speed CMOS full adder circuits for low voltage VLSI design

S Wairya, RK Nagaria, S Tiwari - International Journal of VLSI …, 2012 - academia.edu
This paper presents comparative study of high-speed, low-power and low voltage full adder
circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A …

Analognet: Convolutional neural network inference on analog focal plane sensor processors

MZ Wong, B Guillard, R Murai, S Saeedi… - arXiv preprint arXiv …, 2020 - arxiv.org
We present a high-speed, energy-efficient Convolutional Neural Network (CNN) architecture
utilising the capabilities of a unique class of devices known as analog Focal Plane Sensor …

Design and performance evaluation of hybrid full adder for extensive PDP reduction

S Janwadkar, S Das - 2018 3rd International Conference for …, 2018 - ieeexplore.ieee.org
Modern VLSI techniques focus greatly on High Speed Propagation and Low Power
Consumption. In this research paper, we present a hybrid 1-bit full adder design which …

DFAL: Diode‐Free Adiabatic Logic Circuits

S Upadhyay, RA Mishra, RK Nagaria… - International Scholarly …, 2013 - Wiley Online Library
The manufacturing advances in semiconductor processing (continually reducing minimum
feature size of transistors, increased complexity and ever increasing number of devices on a …

Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

N Yadav, S Khandelwal… - … Conference on Control …, 2013 - ieeexplore.ieee.org
The conventional single-gate MOSFETs faces great challenges in scaling down of devices
due to the severe short-channel effects that reason an exponential gain in the leakage …

Energy efficient high performance adder/subtractor circuits

G Ramesh, P Manikandan, P Naveen… - … on Smart Electronics …, 2022 - ieeexplore.ieee.org
Integrated circuit has been widely used in different applications. The design and
development of CMOS transistor provides various advantages such as low power …

Optimized approach for reversible code converters using quantum dot cellular automata

NK Misra, S Wairya, VK Singh - … of the 4th International Conference on …, 2016 - Springer
Reversible logic has gained importance in the present development of low-power and high-
speed digital systems in nanotechnology. In this manuscript, we have introduced and …

Low-power dual-vt 7T SRAM bit-cell with reduced area and leakage

S Yadav, Y Bansal, B Joseph… - 2022 IEEE Delhi Section …, 2022 - ieeexplore.ieee.org
This paper proposes a dual-Vt 7T SRAM with a distinct read leakage path. The proposed
dual-Vt 7T SRAM features low leakage current because of its single-ended operation which …

Low‐Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

S Upadhyay, RK Nagaria, RA Mishra - VLSI Design, 2013 - Wiley Online Library
Efficiency of adiabatic logic circuits is determined by the adiabatic and non‐adiabatic losses
incurred by them during the charging and recovery operations. The lesser will be these …