VLSI implementation of fully parallel LTE turbo decoders
Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable
iterative forward error correction. However, owing to the serial data dependence imposed by …
iterative forward error correction. However, owing to the serial data dependence imposed by …
A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks
L Li, RG Maunder, BM Al-Hashimi… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
Turbo codes have recently been considered for energy-constrained wireless communication
applications, since they facilitate a low transmission energy consumption. However, in order …
applications, since they facilitate a low transmission energy consumption. However, in order …
Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system
CC Wong, HC Chang - … Transactions on Circuits and Systems II …, 2010 - ieeexplore.ieee.org
This brief presents a parallel architecture for the turbo decoder using the quadratic
permutation polynomial interleaver. The supported block size ranges from 40 to 6144 with …
permutation polynomial interleaver. The supported block size ranges from 40 to 6144 with …
1.5 Gbit/s FPGA implementation of a fully-parallel turbo decoder designed for mission-critical machine-type communication applications
In wireless communication schemes, turbo codes facilitate near-capacity transmission
throughputs by achieving reliable forward error correction. However, owing to the serial data …
throughputs by achieving reliable forward error correction. However, owing to the serial data …
A flexible LDPC/turbo decoder architecture
Y Sun, JR Cavallaro - Journal of Signal Processing Systems, 2011 - Springer
Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most
powerful error correcting codes that are widely used in modern communication systems. In a …
powerful error correcting codes that are widely used in modern communication systems. In a …
Low latency parallel turbo decoding implementation for future terrestrial broadcasting systems
H Luo, Y Zhang, W Li, LK Huang… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
As a class of high-performance forward error correction codes, turbo codes, which can
approach the channel capacity, could become a candidate of the coding methods in future …
approach the channel capacity, could become a candidate of the coding methods in future …
An improved low-power high-throughput log-MAP turbo decoder
SM Karim, I Chakrabarti - IEEE Transactions on Consumer …, 2010 - ieeexplore.ieee.org
This paper presents an efficient implementation of a high-throughput low-power turbo
decoder. The design of the component decoder has been optimized so as to achieve low …
decoder. The design of the component decoder has been optimized so as to achieve low …
A 6.6 pj/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture
KT Shr, YC Chang, CY Lin… - IEEE Asian Solid-State …, 2011 - ieeexplore.ieee.org
Next-generation communication systems, such as 3GPP-LTE and WiMAX, have adopted
turbo code as the channel coding technique. Turbo decoder usually requires many MAP …
turbo code as the channel coding technique. Turbo decoder usually requires many MAP …
[PDF][PDF] Design and FPGA implementation of power efficient turbo decoder for 4G LTE standards
KN Manjunatha, VA Meshram - International Journal of Applied …, 2017 - researchgate.net
The wireless communication has two significant blocks across transmitter and receivers are
encoders and decoders. This work focuses on the design and implementation of turbo …
encoders and decoders. This work focuses on the design and implementation of turbo …
High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver
SM Karim, I Chakrabarti - IET communications, 2012 - IET
Novel high-throughput architecture for a turbo decoder, which has been conceived by
combining the advantages of pipelining and parallel processing, is proposed. Increase in …
combining the advantages of pipelining and parallel processing, is proposed. Increase in …