Wallflower: Principles and practice of background maintenance

K Toyama, J Krumm, B Brumitt… - Proceedings of the …, 1999 - ieeexplore.ieee.org
Background maintenance is a frequent element of video surveillance systems. We develop
Wallflower, a three-component system for background maintenance: the pixel-level …

[图书][B] VLSI test principles and architectures: design for testability

LT Wang, CW Wu, X Wen - 2006 - books.google.com
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Exclusive test and its applications to fault diagnosis

VD Agrawal, DH Baik, YC Kim… - … Conference on VLSI …, 2003 - ieeexplore.ieee.org
We introduce a new type of test, called exclusive test, and discuss its application to fault
diagnosis in combinational circuits. A test that detects exactly one fault from a given pair of …

[PDF][PDF] Fault collapsing via functional dominance

VD Agrawal, A Prasad, MV Atre - ITC, 2003 - Citeseer
A fault fj is said to dominate another fault fi if all tests for fi detect fj. When two faults dominate
each other, they are called equivalent. Dominance and equivalence relations among faults …

Diagnostic test generation for transition faults using a stuck-at ATPG tool

Y Higami, Y Kurose, S Ohno… - 2009 International …, 2009 - ieeexplore.ieee.org
This paper presents a diagnostic test generation method for transition faults. As two
consecutive vectors application mechanism, launch on capture test is considered. The …

Fault equivalence identification using redundancy information and static and dynamic extraction

ME Amyeen, WK Fuchs, I Pomeranz… - … 19th IEEE VLSI Test …, 2001 - ieeexplore.ieee.org
A procedure for identifying functionally equivalent faults and improving the performance of
diagnostic test pattern generation is described in this paper. The procedure is based on …

Functional fault equivalence and diagnostic test generation in combinational logic circuits using conventional ATPG

A Veneris, R Chang, MS Abadir, S Seyedi - Journal of Electronic Testing, 2005 - Springer
Fault equivalence is an essential concept in digital design with significance in fault
diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper …

Mining global constraints for improving bounded sequential equivalence checking

W Wu, MS Hsiao - Proceedings of the 43rd annual Design Automation …, 2006 - dl.acm.org
In this paper, we propose a novel technique on mining relationships in a sequential circuit to
discover global constraints. In contrast to the traditional learning methods, our mining …

Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation

X Yu, ME Amyeen, S Venkataraman… - … . 21st VLSI Test …, 2003 - ieeexplore.ieee.org
Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator
and an equivalence identification tool. Diagnostic fault simulation can be an expensive …

Diagnostic test pattern generation and fault simulation for stuck-at and transition faults

Y Zhang - 2012 - search.proquest.com
In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for
Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which …