Dramatic improvements in SAT solver technology over the last decade and the growing
need for more efficient and scalable verification solutions have fueled research in …

Figure 1 shows the various steps of the search component. Given a set of query keywords,
the system first uses the symbol table to determine the locations within the database where …

The paper presents several improvements to state-of-the-art in FPGA technology mapping
exemplified by a recent advanced technology mapper DAOmap [Chen and Cong …

The paper explores several ways to improve the speed and capacity of combinational
equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use …

Technology mapping, based on directed acyclic graph covering, suffers from the problem of
structural bias: The structure of the mapped netlist depends strongly on the subject graph. In …

Parameterized heuristics abound in computer aided design and verification, and manual
tuning of the respective parameters is difficult and time-consuming. Very recent results from …

Recent research results have shown that the traditional structural testing for delay and
crosstalk faults may result in over-testing due to the non-trivial number of such faults that are …

We present a method for translating Boolean formulas to CNF by identifying gates with
fanout count of 1, and merging them with their fanout gate to generate a single set of …

This paper describes an efficient implementation of sequential synthesis that uses induction
to detect and merge sequentially-equivalent nodes. State-encoding, scan chains, and test …

We present a SAT-based ATPG tool targeting on a path-oriented transition fault model.
Under this fault model, a transition fault is detected through the longest sensitizable path. In …