This article proposes a solution to the integrated problem of Through-Silicon Via (TSV) placement and mapping of cores to the routers in a three-dimensional mesh-based Network …
Y Gan, H Guo, Z Zhou - Micromachines, 2021 - mdpi.com
Power optimization is an important part of network-on-chip (NoC) design. This paper proposes an improved algorithm based on genetic algorithm on how to properly map IP …
X Weng, Y Liu, C Xu, X Lin, L Zhan, S Wang, D Chen… - Symmetry, 2023 - mdpi.com
Network on chip (NoC) is a promising solution to the challenge of multi-core System-on-Chip (SoC) communication design. Application mapping is the first and most important step in the …
The total number of cores on a single chip is increased due to the rapidly decreasing size of transistors. In order to meet the performance demands of these designs, many designers …
W Xiaodong, L Yi, Y Yintang - IET Computers & Digital …, 2020 - Wiley Online Library
With the development of network‐on‐chip (NoC) theory, lots of mapping algorithm have been proposed to solve the application mapping problem which is an NP‐hard (non …
H Ying, T Hollstein, K Hofmann - … International Conference on …, 2013 - ieeexplore.ieee.org
As the embedded system design focus moving from computation-centric to communication- centric, Networks-on-Chip (NoCs) have been selected as the next generation interconnect …
K Heid, H Ying, C Hochberger… - 2014 9th International …, 2014 - ieeexplore.ieee.org
In this paper a new latency analysis method for wormhole switched Networks-on-Chip is presented. This method can be used for many wormhole switched NoC with flit interleaving …