A classification and evaluation framework for NoC mapping strategies

T Nesrine, B Djamel, M Ali - Journal of Circuits, Systems and …, 2017 - World Scientific
Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs).
In an SoC, the placement of the communicating elements across the network has an impact …

Integrated through-silicon via placement and application mapping for 3D mesh-based NoC design

K Manna, S Swami, S Chattopadhyay… - ACM Transactions on …, 2016 - dl.acm.org
This article proposes a solution to the integrated problem of Through-Silicon Via (TSV)
placement and mapping of cores to the routers in a three-dimensional mesh-based Network …

3D NoC low-power mapping optimization based on improved genetic algorithm

Y Gan, H Guo, Z Zhou - Micromachines, 2021 - mdpi.com
Power optimization is an important part of network-on-chip (NoC) design. This paper
proposes an improved algorithm based on genetic algorithm on how to properly map IP …

A Machine Learning Mapping Algorithm for NoC Optimization

X Weng, Y Liu, C Xu, X Lin, L Zhan, S Wang, D Chen… - Symmetry, 2023 - mdpi.com
Network on chip (NoC) is a promising solution to the challenge of multi-core System-on-Chip
(SoC) communication design. Application mapping is the first and most important step in the …

An Artificial Bee Colony Based Mapping Method for Three Dimensional Network-on-Chip

P Kullu, S Yigit-Sert, M Ozkan-Okay… - … on Emerging Trends in …, 2023 - ieeexplore.ieee.org
The total number of cores on a single chip is increased due to the rapidly decreasing size of
transistors. In order to meet the performance demands of these designs, many designers …

Network‐on‐chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation

W Xiaodong, L Yi, Y Yintang - IET Computers & Digital …, 2020 - Wiley Online Library
With the development of network‐on‐chip (NoC) theory, lots of mapping algorithm have
been proposed to solve the application mapping problem which is an NP‐hard (non …

GSNoC—The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems

H Ying, T Hollstein, K Hofmann - … International Conference on …, 2013 - ieeexplore.ieee.org
As the embedded system design focus moving from computation-centric to communication-
centric, Networks-on-Chip (NoCs) have been selected as the next generation interconnect …

LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip

K Heid, H Ying, C Hochberger… - 2014 9th International …, 2014 - ieeexplore.ieee.org
In this paper a new latency analysis method for wormhole switched Networks-on-Chip is
presented. This method can be used for many wormhole switched NoC with flit interleaving …

[引用][C] 三维片上网络研究综述

张大坤, 黄翠, 宋国治 - 软件学报, 2015

[引用][C] Survey on three-dimensional network-on-chip

张大坤, 黄翠, 宋国治 - Journal of Software, 2015