Trending IC design directions in 2022
For the non-stop demands for a better and smarter society, the number of electronic devices
keeps increasing exponentially; and the computation power, communication data rate, smart …
keeps increasing exponentially; and the computation power, communication data rate, smart …
Technical survey of end-to-end signal processing in BCIs using invasive MEAs
A Erbslöh, L Buron, Z Ur-Rehman… - Journal of Neural …, 2024 - iopscience.iop.org
Modern brain-computer interfaces and neural implants allow interaction between the tissue,
the user and the environment, where people suffer from neurodegenerative diseases or …
the user and the environment, where people suffer from neurodegenerative diseases or …
A 7.3-μ w 13-enob 98-db sfdr noise-shaping sar adc with duty-cycled amplifier and mismatch error shaping
This article presents a second-order noise-shaping successive-approximation-register
(SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital …
(SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital …
An 871 nW 96.2 dB SNDR pipelined second-order noise-shaping SAR ADC employing charge-efficient CLS-assisted residue amplifier
This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-
register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution …
register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution …
Cryptographic transistor for true random number generator with low power consumption
We design a cryptographic transistor (cryptoristor)–based true random number generator
(tRNG) with low power consumption and small footprint. This is the first attempt to use …
(tRNG) with low power consumption and small footprint. This is the first attempt to use …
A 93.6-dB SNDR Fully Dynamic CT–DT Noise-Shaping SAR ADC With Closed-Loop Capacitively Coupled Two-Stage FIA
L Meng, S Song, M Zhao, Z Tan - IEEE Journal of Solid-State …, 2024 - ieeexplore.ieee.org
This article presents an embedded-friendly high-precision two-step noise-shaping (NS)
successive approximation register (SAR) analog-to-digital converter (ADC) designed for …
successive approximation register (SAR) analog-to-digital converter (ADC) designed for …
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
To design a low-oversampled high-resolution noise-shaping successive approximation
register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be …
register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be …
Oversampling ADC: A Review of Recent Design Trends
A Verreault, PV Cicek, A Robichaud - IEEE Access, 2024 - ieeexplore.ieee.org
Oversampling analog-to-digital converters (ADC) serve as the backbone of high-
performance, high-precision data interfaces, owing to their remarkable ability to filter out …
performance, high-precision data interfaces, owing to their remarkable ability to filter out …
SAR-Assisted Energy-Efficient Hybrid ADCs
The distinct advantages of low power consumption and hardware compactness make SAR
ADCs especially appealing in scaled CMOS technologies, garnering significant attention …
ADCs especially appealing in scaled CMOS technologies, garnering significant attention …
A 40 kS/sCalibration-Free Incremental△ Σ ADC Achieving 104 dB DR and 105.7 dB SFDR
MA Mokhtar, O Ismail, P Vogelmann… - … 2023-IEEE 49th …, 2023 - ieeexplore.ieee.org
High dynamic range (DR) Nyquist-rate ADCs are needed in many sensing applications.
While noise-and mismatch-error shaping realize power efficient designs, they prevent true …
While noise-and mismatch-error shaping realize power efficient designs, they prevent true …