Wafer-to-wafer bonding is becoming a critical unit process step with the increase in the
demand for 3D integration. The widely used bonding method is plasma activated bonding …

In this letter, we demonstrate three-dimensional (3D) stacked InGaAs high-electron-mobility
transistors (HEMTs) on Si with back metal for a monolithic 3D RF platform. The devices are …

Low-temperature Schottky barrier (SB) metal oxide semiconductor field-effect transistors
(MOSFETs) were investigated as top-level devices for monolithic three-dimensional (M3D) …

Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™
development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin …

Beyond MBCFET TM technology, the 3-dimensional stacked FET (3DSFET) emerges as a
promising contender, featuring a structure that stacks NMOS and PMOS vertically to …

We describe challenges of the epitaxial Si-cap/Si 0.75 Ge 0.25//Si-substrate growth process,
in view of its application in 3D device integration schemes using Si 0.75 Ge 0.25 as …

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-
controlled-grain technique and several innovative low-thermal budget processes, including …

Abstract Sequential 3D (S3D) integration has been identified as a potential candidate for
area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other …

Future mobile communication systems and 5G base stations are relying on the availability of
a variety of high-speed high-performing semiconductor technologies. Not only advanced …

By using classical molecular dynamics simulations and a novel technique to identify defects
based on the calculation of atomic strain, we have elucidated the detailed mechanisms …