The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

Increasing integrated-circuit pin bandwidth has motivateda corresponding increase in the
degree or radix of interconnection networksand their routers. This paper introduces the …

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip
applications. The transceiver employs a number of features for reducing power …

A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is
presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 …

To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in
CMOS transistors, this paper explores the design of integrated circuits based on nano …

We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps
operation over single-board and backplane FR4 channels with power efficiencies between …

A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is
reported. Based on expected channel characteristics, the proposed I/O features low …

This application is a continuation of US application Ser. No. 11/177,095 filed on Jul. 8, 2005
which claims the benefit of the filing date of US Provisional Patent Application No …

High-speed signaling over high density interconnect on organic package substrates or
silicon interposers offers an attractive solution to the off-chip bandwidth limitation problem …

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial
link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock …