Methods and systems are described for receiving N phases of a local clock signal and M
phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an …

Orthogonal differential vector signaling codes are described which support encoded sub-
channels allowing transport of distinct data and clocking signals over the same transport …

Methods and systems are described for receiving signal elements corresponding to a first
group of symbols of a vector signaling codeword over a first densely-routed wire group of a …

Methods and systems described include a first dielectric material having a plurality of
embedded conductors of a multi-wire channel, the plurality of embedded conductors …

Systems and methods are described for transmitting data over physical channels to provide
a high bandwidth, low latency interface between integrated circuit chips with low power …

Pre-charging two or more sets of nodes to set a differential output of a multi-input summation
latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets …

Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS)
clock and data recovery circuits having configurable sub-channel multi-input comparator …

Systems and methods are described for transmitting data over physical channels to provide
a high bandwidth, low latency interface between a transmitting device and a receiv ing …

Described herein are systems and methods of receiving first and second input signals at a
first two-input comparator, responsively generating a first subchannel output, receiving third …

Methods and systems are described for generating two comparator outputs by comparing a
received signal to a first threshold and a second threshold according to a sampling clock, the …