Fabrication and electrical characteristics of a novel interposer with polymer liner and silicon pillars with ultra-low-resistivity as through-silicon-vias (TSVs) for 2.5 D/3D …
QW Chen, YY Yan, YT Ding, SW Wang… - Microsystem …, 2015 - Springer
Motivated by the desire of process simplicity and feasibility for 2.5 D/3D integration, a novel
interposer technique with polymer liner and silicon pillars of ultra-low-resistivity as through …
interposer technique with polymer liner and silicon pillars of ultra-low-resistivity as through …
3D ring oscillator based test structures to detect a Trojan Die in a 3D die stack in the presence of process variations
3D integrated circuits introduce both advantages and disadvantages for security. Among the
disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between …
disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between …
Test structure for electrical characterization of copper nanowire anisotropic conductive film (NW-ACF) for 3D stacking applications
Copper nanowire arrays (~ 200 nm diameter) grown in porous polymer template is a
potential low temperature interconnection technology compared to metal/metal or solder …
potential low temperature interconnection technology compared to metal/metal or solder …
Detecting a Trojan Die in Three-Dimensional Stacked Integrated Circuits
SA Alhelaly - 2017 - search.proquest.com
Abstract Three-dimensional (3D) integrated circuits (ICs) aim to further increase integration
density beyond Moore's Law, enhance system performance, and reduce interconnect …
density beyond Moore's Law, enhance system performance, and reduce interconnect …