An area efficient network on chip architecture using high performance pipelines FIFO technique
S Sariga, C Nandagopal - 2017 IEEE International Conference …, 2017 - ieeexplore.ieee.org
Most correspondence movement in today's Network on Chips (NOC) depends on switch for
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
[PDF][PDF] Variable Latency Approach in VLSI Adder Implemented to Reduce Area and Power
K Kaarthik, C Vivek - Indian Journal …, 2018 - sciresol.s3.us-east-2.amazonaws …
Abstract Objective: The Ultimate aim of the VLSI Design is to improve the efficiency,
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
The motivations and outcomes of consumer engagement with online sexual health communities
H Du - 2022 - theses.ncl.ac.uk
The continuous improvement in living standards has resulted in increasing attention being
paid to personal health. The definition of health nowadays no longer refers only to physical …
paid to personal health. The definition of health nowadays no longer refers only to physical …
[PDF][PDF] Design of Absolute Position Encoder
P Kirubha, R Loganayaki, S Logesh - Journal of Chemical and … - chettinadtech.ac.in
The target of the plan is supreme position encoder can be associated with the Input and
yield signals which considers an immediate interface to the host processor and to run the …
yield signals which considers an immediate interface to the host processor and to run the …
Analysis on Improving Network Security Through Relaying Techniques.
SP Rajan, M Paranthaman - International Journal of …, 2018 - search.ebscohost.com
Portable Internet that has the gigantic prevalence, or, in other words benefits in an anchored
way that, has turned into a perilous issue. Physical layer security (PHY-security) has been …
way that, has turned into a perilous issue. Physical layer security (PHY-security) has been …
[引用][C] Performance Comparison in Topological Design of Low Power CMOS Full Adder Circuits
KS Swetha, M Mangaiyarkarasi, M Chitravalavan
[引用][C] Prototype of a Wearable System for Remote Fetal Monitoring During Pregnancy
P Prabha, R Priyadharsini, N Priyanka, C Ramya… - Journal of Chemical and …
[引用][C] Design of Low Power Content-Addressable Memory using Master–Slave Match Line
P Nithya, S Tamilselvan - Journal of Chemical and Pharmaceutical Sciences …