We review recent developments in directly modulated lasers (DMLs) with low operating
energy for datacom and computercom applications. Key issues are their operating energy …

Recent changes in CMOS device structures and materials motivated by impending atomistic
and quantum-mechanical limitations have profoundly influenced the nature of delay and …

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip
communications over high-loss electrical channels such as backplanes. The equalization …

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that
operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse …

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To
mitigate the effects of channel loss and other impairments, a 5-tap decision feedback …

A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been
demonstrated in a 0.13-mum CMOS SOI technology. The transceiver integrates …

A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is
reported. Based on expected channel characteristics, the proposed I/O features low …

This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward
equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the …

This study provides a comprehensive review of decision feedback equalisation (DFE) for
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …

A 4-channel 1.25-10.3 Gb/s backplane transceiver macro with an adaptive analog linear
equalizer (LE) and 1-tap speculative decision-feedback equalizer (DFE) receiver (Rx) and a …