[图书][B] Handbook of approximation algorithms and metaheuristics

TF Gonzalez - 2007 - taylorfrancis.com
Delineating the tremendous growth in this area, the Handbook of Approximation Algorithms
and Metaheuristics covers fundamental, theoretical topics as well as advanced, practical …

[图书][B] Computer-aided reasoning: ACL2 case studies

M Kaufmann, P Manolios, JS Moore - 2013 - books.google.com
Computer-Aided Reasoning: ACL2 Case Studies illustrates how the computer-aided
reasoning system ACL2 can be used in productive and innovative ways to design, build, and …

[PDF][PDF] Efficient algorithms for clause-learning SAT solvers

L Ryan - 2004 - summit.sfu.ca
Boolean satisfiability (SAT) is NP-complete. No known algorithm for SAT is of polynomial
time complexity. Yet, many of the SAT instances generated as a means of solving real-world …

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW

MN Velev, RE Bryant - Proceedings of the 38th annual design …, 2001 - dl.acm.org
We compare SAT-checkers and decision diagrams on the evalua-tion of Boolean formulas
produced in the formal verification of both correct and buggy versions of superscalar and …

Parameterized verification with automatically computed inductive assertions?

T Arons, A Pnueli, S Ruah, Y Xu, L Zuck - … CAV 2001 Paris, France, July 18 …, 2001 - Springer
The paper presents a method, called the method of verification by invisible invariants, for the
automatic verification of a large class of parameterized systems. The method is based on the …

Boolean satisfiability in electronic design automation

JP Marques-Silva, KA Sakallah - Proceedings of the 37th Annual Design …, 2000 - dl.acm.org
Boolean Satisfiability (SAT) is often used as the underlying model for a significant and
increasing number of applications in Electronic Design Automation (EDA) as well as in many …

A comparative study of two Boolean formulations of FPGA detailed routing constraints

GJ Nam, F Aloul, K Sakallah, R Rutenbar - Proceedings of the 2001 …, 2001 - dl.acm.org
A Boolean-based router expresses the routing constraints as a Bool? ean function which is
satisfiable if and only if the layout is routable. Compared to traditional routers, Boolean …

Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

RE Bryant, S German, MN Velev - ACM Transactions on Computational …, 2001 - dl.acm.org
The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the
manipulation of data by a processor when verifying the correctness of its control logic. By …

Putting it all together–Formal verification of the VAMP

S Beyer, C Jacobi, D Kröning, D Leinenbach… - International Journal on …, 2006 - Springer
In the verified architecture microprocessor (VAMP) project we have designed, functionally
verified, and synthesized a processor with full DLX instruction set, delayed branch …

Efficient translation of Boolean formulas to CNF in formal verification of microprocessors

MN Velev - ASP-DAC 2004: Asia and South Pacific Design …, 2004 - ieeexplore.ieee.org
We present a method for translating Boolean formulas to CNF by identifying gates with
fanout count of 1, and merging them with their fanout gate to generate a single set of …