Multiple-valued logic—Its status and its future
Hurst - IEEE Transactions on computers, 1984 - ieeexplore.ieee.org
Multiple-valued logic, in which the number of discrete logic levels is not confined to two, has
been the subject of much research over many years. The practical objective of this work has …
been the subject of much research over many years. The practical objective of this work has …
The prospects for multivalued logic: A technology and applications view
KC Smith - IEEE Transactions on Computers, 1981 - ieeexplore.ieee.org
Advances in multiple-valued logic (MVL) have been inspired, in large part, by advances in
integrated circuit technology. Multiple-valued logic has matured to the point where four …
integrated circuit technology. Multiple-valued logic has matured to the point where four …
Realization of quaternary logic circuits by n-channel MOS devices
Y Yasuda, Y Tokuda, S Zaima, K Pak… - IEEE Journal of Solid …, 1986 - ieeexplore.ieee.org
A method to implement quaternary circuits using NMOS devices is proposed. The authors
have designed a simplified elementary form of inverter and have implemented a series of …
have designed a simplified elementary form of inverter and have implemented a series of …
Memristor-CNTFET based ternary logic gates
NS Soliman, ME Fouda, AG Radwan - Microelectronics journal, 2018 - Elsevier
Multilevel electronic systems offer the reduction of implementation'complexity, power
consumption, and area. Ternary system is a very promising system where more information …
consumption, and area. Ternary system is a very promising system where more information …
A novel voltage-mode CMOS quaternary logic design
RCG da Silva, H Boudinov… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold
voltage transistors and three power supply lines to implement quaternary logic gates …
voltage transistors and three power supply lines to implement quaternary logic gates …
Polarization encoded all-optical quaternary R–S flip-flop using binary latch
The developments of different multi-valued logic (MVL) systems have received considerable
interests in recent years all over the world. In electronics, efforts have already been made to …
interests in recent years all over the world. In electronics, efforts have already been made to …
All-optical quaternary logic based information processing: challenges and opportunities
JN Roy, T Chattopadhyay - Design and architectures for digital …, 2013 - books.google.com
Science and Technology is providing people all over the world with much better ways of
communicating than ever before, and the winds of change have whipped up the de‐-sire to …
communicating than ever before, and the winds of change have whipped up the de‐-sire to …
Implementation of multi-valued logic gates using full current-mode CMOS circuits
In this paper, a novel multi-valued logic gate set is designed by using only current-mode
CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based …
CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based …
Complete logic family using tunneling-phase-logic devices
HAH Fahmy, RA Kiehl - ICM'99. Proceedings. Eleventh …, 1999 - ieeexplore.ieee.org
This paper presents the work done to develop and characterize the behavior of binary
tunneling phase logic (TPL) devices. Three input NAND, NOR and MINORITY functions are …
tunneling phase logic (TPL) devices. Three input NAND, NOR and MINORITY functions are …
An all-optical technique for a binary-to-quaternary encoder and a quaternary-to-binary decoder
T Chattopadhyay, JN Roy - Journal of Optics A: Pure and Applied …, 2009 - iopscience.iop.org
A polarization encoded all-optical scheme for a binary-(radix= 2)-to-quaternary (radix= 4)
encoder and a quaternary-to-binary decoder is proposed and described. The performance …
encoder and a quaternary-to-binary decoder is proposed and described. The performance …