System and method for an improved fine pitch joint

CT Chen, LU Wen-Hsiung, MD Cheng, CS Liu… - US Patent …, 2016 - Google Patents
BACKGROUND Semiconductor devices are used in a variety of electronic applications, such
as personal computers, cellphones, digital cameras, and other electronic equipment, as …

Electrical connections for chip scale packaging

HW Chen, SW Liang - US Patent 8,912,668, 2014 - Google Patents
Electrical connections for chip scale packaging are disclosed. In one embodiment, a
semiconductor device includes a post passivation layer disposed overa Substrate, the …

Packaging devices, methods of manufacture thereof, and packaging methods

HW Chen, TY Yu - US Patent 9,401,308, 2016 - Google Patents
Packaging devices, methods of manufacture thereof, and packaging methods are disclosed.
In some embodiments, a packaging device includes a first substrate including a post …

Bonded structures for package and substrate

MH Cha, C Chuang, YC Chuang, HJ Liu… - US Patent …, 2015 - Google Patents
The embodiments described provide elongated bonded structures near edges of packaged
structures free of solder wetting on sides of copper posts substantially facing the center of …

Bond structures and the methods of forming the same

CH Yu, WC Chiou, MF Chen, YH Chen - US Patent 9,893,028, 2018 - Google Patents
A method includes forming a first conductive feature and a second conductive feature,
forming a metal pad over and electrically connected to the first conductive feature, and …

Bump on pad (BOP) bonding structure

YC Chuang, C Chuang, CC Kuo, CS Chen - US Patent 9,196,573, 2015 - Google Patents
The embodiments described above provide enlarged overlap ping Surface areas of bonding
structures between a package and a bonding Substrate. By using elongated bonding struc …

Electrical connections for chip scale packaging

HW Chen, SW Liang - US Patent 9,224,680, 2015 - Google Patents
Electrical connections for chip scale packaging are disclosed. In one embodiment, a
semiconductor device includes a post-passivation layer disposed over a substrate, the …

Electrical connection for chip scale packaging

MC Yew, WY Lin, FJ Li, PY Lin - US Patent 9,548,281, 2017 - Google Patents
BACKGROUND Generally, a semiconductor die may be connected to other devices external
to the semiconductor die through a type of packaging utilizing solder bumps. The Solder …

Interconnect joint protective layer apparatus and method

CT Chen, HT Kuo, HW Chen, LU Wen-Hsiung… - US Patent …, 2018 - Google Patents
Disclosed herein is a mechanism for forming an interconnect comprising forming a
connector on an interconnect disposed on a first surface of a first substrate and applying a …

Bonded structures for package and substrate

MH Cha, CS Chen, CC Kuo, TH Chiang, HJ Liu… - US Patent …, 2017 - Google Patents
Related US Application Data which is a continuation of application No. 14/480, 439, filed on
Sep. 8, 2014, now Pat. No. 9,123,788, which is a continuation of application No. 13/667 …