Strategies for reducing decoding cycles in stochastic LDPC decoders

D Wu, Y Chen, Q Zhang, Y Ueng… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This brief presents three strategies, including initialization based on Look Up Table (LUT),
postprocessing based on bit flipping and hard decision based on the posterior information …

Latency-optimized stochastic LDPC decoder for high-throughput applications

D Wu, Y Chen, Q Zhang, L Zheng… - … on Circuits and …, 2015 - ieeexplore.ieee.org
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve
high throughput with less area. However, most architectures suffer from large decoding …

A modular architecture for structured long block-length LDPC decoders

AJ Wong, S Hemati, WJ Gross - Journal of Signal Processing Systems, 2018 - Springer
High-speed, low-area decoders for low-density parity-check (LDPC) codes with long block
lengths are challenging to implement due to the large amount of nodes and edges required …