Low-power electronic technologies for harsh radiation environments

J Prinzie, FM Simanjuntak, P Leroux… - Nature Electronics, 2021 - nature.com
Electronic technologies that can operate in harsh radiation environments are important in
space, nuclear and avionic applications. However, radiation-hardened (rad-hard) integrated …

Ionizing radiation damage in 65 nm CMOS technology: Influence of geometry, bias and temperature at ultra-high doses

G Borghello, E Lerario, F Faccio, HD Koch… - Microelectronics …, 2021 - Elsevier
We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-
high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of …

Ionizing radiation effects in nanoscale CMOS technologies exposed to ultra-high doses

G Borghello - 2019 - air.uniud.it
This thesis studies the effects of radiation in nanoscale CMOS technologies exposed to ultra-
high total ionizing doses (TID), up to 1 Grad (SiO2). These extreme radiation levels are …

Modeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOS

A Nikolaou, M Bucher, N Makris… - 2018 International …, 2018 - ieeexplore.ieee.org
High doses of ionizing radiation drastically impair the electrical performance of CMOS
technology. Enclosed gate layout remains an effective means to reduce this impact …

Investigation of scaling and temperature effects in total ionizing dose (TID) experiments in 65 nm CMOS

L Chevas, A Nikolaou, M Bucher… - … " Mixed Design of …, 2018 - ieeexplore.ieee.org
Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron
Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages …

ICT device impacts and development trends on cosmic radiation environment

Y Yi, SK Jeong, I Hwang, YS Yang… - Electronics and …, 2022 - koreascience.kr
Cosmic radiation environments having extremely high-energy particles and photons cause
severe malfunctions of electrical components in space and terrestrial regions. In this study …

Design and Characterization of a Picosecond Timing ASIC in 55-nm CMOS

B Lu, J Huo, X Jiang, H Li, X Yan… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
For more than two decades, amplifier–discriminator application-specific integrated circuits
(ASICs) have been demonstrated to be the optimal choice for time measurement in high …

Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions

CM Andreou, DM González-Castaño, S Gerardin… - Electronics, 2019 - mdpi.com
The radiation tolerance of subthreshold reference circuits for space microelectronics is
presented. The assessment is supported by measured results of total ionization dose and …

Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication

JW Yeon, SS Yoon, HJ Park, TH Kil… - … on Device and …, 2024 - ieeexplore.ieee.org
High-pressure deuterium annealing (HPDA) has been proposed as a promising process to
enhance device performance and reliability. However, additional thermal stress after the …

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

D Ki, M Lee, N Lee, S Cho - Electronics, 2023 - mdpi.com
This study designed a radiation-hardened (RH) complementary metal oxide semiconductor
(CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to …