BeGAN: Power grid benchmark generation using a process-portable GAN-based methodology
Evaluating CAD solutions to physical implementation problems has been extremely
challenging due to the unavailability of modern benchmarks in the public domain. This work …
challenging due to the unavailability of modern benchmarks in the public domain. This work …
Full chip impact study of power delivery network designs in monolithic 3D ICs
In this paper, we present a comprehensive study on the impact of power delivery network
(PDN) on full-chip wirelength, routability, power, and thermal effects in monolithic 3D ICs …
(PDN) on full-chip wirelength, routability, power, and thermal effects in monolithic 3D ICs …
Full chip impact study of power delivery network designs in gate-level monolithic 3-D ICs
In this paper, we present a comprehensive study on the impact of power delivery network
(PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic …
(PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic …
SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
Designing the power delivery network (PDN) in very large-scale integrated (VLSI) circuits is
increasingly important, especially for nowadays low-power integrated circuit (IC) design. In …
increasingly important, especially for nowadays low-power integrated circuit (IC) design. In …
Efficient region-aware P/G TSV planning for 3D ICs
Power delivery network (PDN) design is one of the most critical challenges in 3D Integrated
Circuits (IC) design. In existing studies, to ensure the robustness of the 3D PDN, the number …
Circuits (IC) design. In existing studies, to ensure the robustness of the 3D PDN, the number …
Actively alleviate power gating-induced power/ground noise using parasitic capacitance of on-chip memories in MPSoC
By integrating multiple processing units (PUs) and memories on a single chip,
multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and …
multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and …
HS3DPG: Hierarchical simulation for 3D P/G network
As different chips are stacked together in 3D ICs, the power/ground (P/G) network simulation
becomes more challenging than that of 2D cases. In this paper, we propose a hierarchical …
becomes more challenging than that of 2D cases. In this paper, we propose a hierarchical …
Novel crack sensor for tsv-based 3d integrated circuits: design and deployment perspectives
The CTE mismatch-induced stress in 3D ICs may initiate cracks from the interface between a
TSV and its dielectric liner, and propagates them on the silicon substrate surface. If a crack …
TSV and its dielectric liner, and propagates them on the silicon substrate surface. If a crack …
HS3-DPG: hierarchical simulation for 3-DP/G network
As different tiers are stacked together in 3-D integrated circuits, the power/ground (P/G)
network simulation becomes more challenging than that of 2-D cases. In this brief, we …
network simulation becomes more challenging than that of 2-D cases. In this brief, we …
Memcomputing: The cape of good hope:[Extended special session description]
Energy efficiency has emerged as a major barrier to performance scalability for modern
processors. On the other hand, significant breakthroughs have been achieved in memory …
processors. On the other hand, significant breakthroughs have been achieved in memory …