Survey of Reliability Research on 3D Packaged Memory

S Zhou, K Ma, Y Wu, P Liu, X Hu, G Nie, Y Ren, B Qiu… - Electronics, 2023 - mdpi.com
As the core carrier of information storage, a semiconductor memory device is a basic product
with a large volume that is widespread in the integrated circuit industry. With the rapid …

The effect of solder joint microstructure on the drop test failure—a peridynamic analysis

J Mehrmashhadi, Y Tang, X Zhao, Z Xu… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
We investigate the drop reliability of different solder joint microstructures using a coupled
board-level finite-element (FE) analysis and the microscale peridynamic (PD) simulations …

Accuracy of simplified printed circuit board finite element models

RA Amy, GS Aglietti, G Richardson - Microelectronics Reliability, 2010 - Elsevier
Electronic components are prone to failure due to shock or vibration loads. To predict when
this failure may occur it is necessary to calculate the vibration response of the printed circuit …

Reliability study of board-level lead-free interconnections under sequential thermal cycling and drop impact

B Zhang, H Ding, X Sheng - Microelectronics Reliability, 2009 - Elsevier
The sequential thermal cycling (TC) and drop impact test are more reasonable to evaluate
the reliability of lead-free solder interconnections compared with separate TC test or drop …

Reliability and failure analysis of SAC 105 and SAC 1205N lead-free solder alloys during drop test events

ML Wu, JS Lan - Microelectronics Reliability, 2018 - Elsevier
The purpose of this study is to establish a predictive fatigue life model for SAC 105 (Sn-1.0
Ag-0.5 Cu) and SAC 1205N (Sn-1.2 Ag-0.5 Cu with nickel) lead-free solder alloys. A …

Cohesive fracture mechanics based numerical analysis to BGA packaging and lead free solders under drop impact

Y Yao, LM Keer - Microelectronics reliability, 2013 - Elsevier
Lead free solders are replacing lead rich solders in the electronic industry, the performance
and safety of lead free solder interconnects in electric packaging under drop impact …

A comprehensive review of drop impact modeling on portable electronic devices

YH Yau, SN Hua - 2011 - asmedigitalcollection.asme.org
This article is dedicated to the review of publications on drop impact analysis performed on
consumer electronic devices such as cellular phones and two-way radios in the past …

Effects of different drop test conditions on board-level reliability of chip-scale packages

YS Lai, PC Yang, CL Yeh - Microelectronics Reliability, 2008 - Elsevier
In this study, reliability performances of board-level chip-scale packages subjected to four
JEDEC drop test conditions: A (500G; 1.0 ms), B (1500G; 0.5 ms), F (900G; 0.7 ms), and H …

Drop impact reliability test and failure analysis for large size high density FOWLP package on package

Z Chen, F Che, MZ Ding, DSW Ho… - 2017 IEEE 67th …, 2017 - ieeexplore.ieee.org
Drop test reliability of the 20 mm× 20 mm RDL-first FOWLP on bottom and 8 mm× 8 mm
WLCSP on top for Package on Package (PoP) test vehicle was validated by the …

Survivability of embedded microelectronics in precision guided projectiles: Modeling and characterization

P Verberne, SA Meguid, EA Elsayed - International Journal of Impact …, 2021 - Elsevier
Precision guided projectiles (PGPs) experience severe shock loads during launch
emanating from the propellant gasses and the surrounding air. Our most recent multiphysics …