Performance improvement of 1T DRAM by raised source and drain engineering
MHR Ansari, S Cho - IEEE Transactions on Electron Devices, 2021 - ieeexplore.ieee.org
In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET)
with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) …
with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) …
Core-shell dual-gate nanowire memory as a synaptic device for neuromorphic application
In this work, a synaptic device for neuromorphic system is proposed and designed to
emulate the biological behaviors in the novel device structure of core-shell dual-gate …
emulate the biological behaviors in the novel device structure of core-shell dual-gate …
Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
1T-DRAM with shell-doped architecture
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …
High Retention With -Oxide- Junctionless Architecture for 1T DRAM
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper reports on the potential benefits of a vertically stacked n-and p-type junctionless
(JL) transistor physically decoupled through an intermediate oxide layer for dynamic …
(JL) transistor physically decoupled through an intermediate oxide layer for dynamic …
More physical understanding of current characteristics of tunneling field-effect transistor leveraged by gate positions and properties through dual-gate and gate-all …
In this work, a tunneling field-effect transistor (TFET) in the structure that can maximize the
electrostatic effects in determining its electrical performances is optimally designed and …
electrostatic effects in determining its electrical performances is optimally designed and …
Improving charge retention in capacitorless DRAM through material and device innovation
MHR Ansari, N Navlakha, JT Lin… - Japanese Journal of …, 2019 - iopscience.iop.org
In this work, we report on the opportunities to enhance the retention time (RT) of an
accumulation mode capacitorless DRAM (1T-DRAM) through appropriate material …
accumulation mode capacitorless DRAM (1T-DRAM) through appropriate material …
TFET based 1T-DRAM: Physics, Significance and Trade-offs
N Navlakha, MHR Ansari… - 2019 IEEE SOI-3D …, 2019 - ieeexplore.ieee.org
The work showcases device physics, the significance and trade-offs of DRAM metrics in a
Tunnel Field Effect Transistor (TFET) based 1T dynamic memory. The analysis shows …
Tunnel Field Effect Transistor (TFET) based 1T dynamic memory. The analysis shows …