Modifying the Power and Performance of 2-Dimensional MoS2 Field Effect Transistors
Over the past 60 years, the semiconductor industry has been the core driver for the
development of information technology, contributing to the birth of integrated circuits …
development of information technology, contributing to the birth of integrated circuits …
Beyond the conventional transistor
HSP Wong - IBM Journal of Research and Development, 2002 - ieeexplore.ieee.org
This paper focuses on approaches to continuing CMOS scaling by introducing new device
structures and new materials. Starting from an analysis of the sources of improvements in …
structures and new materials. Starting from an analysis of the sources of improvements in …
Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs
N Mohankumar, B Syamal… - IEEE transactions on …, 2010 - ieeexplore.ieee.org
The design of analog and RF circuits in CMOS technology has become increasingly more
difficult as device modeling faces new challenges in the deep-submicrometer regime and …
difficult as device modeling faces new challenges in the deep-submicrometer regime and …
Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors
We demonstrate that carrier scattering induced by the thickness fluctuation of a silicon-on-
insulator (SOI) film reduces electron mobility in ultrathin-body metal–oxide–semiconductor …
insulator (SOI) film reduces electron mobility in ultrathin-body metal–oxide–semiconductor …
Two gates are better than one [double-gate MOSFET process]
PM Solomon, KW Guarini, Y Zhang… - IEEE circuits and …, 2003 - ieeexplore.ieee.org
A planar self-aligned double-gate MOSFET process has been implemented where a unique
sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer …
sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer …
Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application
D Esseni, M Mastrapasqua, GK Celler… - … on Electron Devices, 2001 - ieeexplore.ieee.org
In this paper, we present a comprehensive experimental characterization of electron and
hole effective mobility (/spl mu//sub eff/) of ultrathin SOI n-and p-MOSFETs. Measurements …
hole effective mobility (/spl mu//sub eff/) of ultrathin SOI n-and p-MOSFETs. Measurements …
Experimental study on electron mobility in ultrathin-body silicon-on-insulator metal-oxide-semiconductor field-effect transistors
The electron mobility in ultrathin-body (UTB) silicon-on-insulator (SOI) metal-oxide-
semiconductor field-effect transistors (MOSFETs) with SOI thicknesses from 2.3 to 60 nm is …
semiconductor field-effect transistors (MOSFETs) with SOI thicknesses from 2.3 to 60 nm is …
[图书][B] Fundamentals of Ultra-thin-body MOSFETs and FinFETs
JG Fossum, VP Trivedi - 2013 - books.google.com
Understand the theory, design and applications of the two principal candidates for the next
mainstream semiconductor-industry device with this concise and clear guide to FD/UTB …
mainstream semiconductor-industry device with this concise and clear guide to FD/UTB …
Analytical modeling of charge plasma-based optimized nanogap embedded surrounding gate MOSFET for label-free biosensing
In this paper, analytical modeling of a charge plasma-based nanogap embedded
surrounding gate MOSFET biosensor for label-free biosensing has been presented and …
surrounding gate MOSFET biosensor for label-free biosensing has been presented and …
Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications
This paper presents a systematic study of the subthreshold analog/RF performance for
underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The …
underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The …