A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated
across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where …

A system clock with a 50% duty cycle is demanded in high-speed data communication
applications, such as double data rate memories and double sampling analog-to-digital …

Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or
if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a …

A wide-frequency all-digital duty cycle corrector with selfadaptive configurable delay chain is
proposed. The proposed circuit can detect the alterations of clock frequency and the …

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2
GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty …

Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate
the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle …

A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate
interface-based DRAM applications is presented. To improve the correction time, this work …

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle
correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a …

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision
pipelined A/D converter. Combined charge pump is used to ensure the stability of the current …

In this paper, a duty cycle corrector (DCC) with a dual loop low pass filter (DLLPF) has been
proposed to improve correction time and noise characteristics. It shows that the correction …