A review on machine learning approaches for predicting the effect of device parameters on performance of nanoscale MOSFETs

R Ghoshhajra, K Biswas… - 2021 Devices for Integrated …, 2021 - ieeexplore.ieee.org
This review investigates the possibility of using Machine Learning as a replacement for
numerical TCAD device simulation. As the chip design is getting complex to incorporate …

Neural approach for modeling and optimizing Si-MOSFET manufacturing

HC Choi, H Yun, JS Yoon, RH Baek - IEEE Access, 2020 - ieeexplore.ieee.org
An optimal design of semiconductor device and its process uniformity are critical factors
affecting desired figure-of-merits as well as reducing fabrication cost of fixing possible …

Sensitivity analysis based on neural network for optimizing device characteristics

MH Oh, MW Kwon, K Park… - IEEE Electron Device …, 2020 - ieeexplore.ieee.org
This letter presents a novel method for the sensitivity analysis between a process parameter
and an electrical characteristic using the gradient of a neural network (NN). As devices …

Cell library characterization using machine learning for design technology co-optimization

F Klemme, Y Chauhan, J Henkel… - Proceedings of the 39th …, 2020 - dl.acm.org
To explore the full potential of any circuit and ensure its functionality at run-time, cell libraries
beyond the typical PVT corners are needed. This holds even more for emerging …

Device performance prediction of nanoscale junctionless FinFET using MISO artificial neural network

R Ghoshhajra, K Biswas, A Sarkar - Silicon, 2022 - Springer
This paper investigates the way to use Multi-layer neural network as a possible replacement
of numerical TCAD device simulation to study device characteristics using limited …

Neural network based design optimization of 14-nm node fully-depleted SOI FET for SoC and 3DIC applications

H Yun, JS Yoon, J Jeong, S Lee… - IEEE Journal of the …, 2020 - ieeexplore.ieee.org
In this article, by using neural network, we proposed a method to optimize Fully-Depleted
(FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off …

Design and system technology co-optimization sensitivity prediction for VLSI technology development using machine learning

CK Cheng, CT Ho, C Holtz, B Lin - 2021 ACM/IEEE …, 2021 - ieeexplore.ieee.org
As technology nodes evolve, geometric pitch scaling starts to slow down. In order to retain
the trend of the Moore's Law, Design Technology Co-Optimization (DTCO) and System …

Ensemble Learning strategy in modeling of future generation nanoscale devices using Machine Learning

R Ghoshhajra, K Biswas, M Sultana… - 2023 IEEE Devices for …, 2023 - ieeexplore.ieee.org
In semiconductor industry, conventional method of device characteristics analysis using
TCAD based simulation is sometimes difficult. TCAD based device simulation gives the …

Machine learning prediction for design and system technology co-optimization sensitivity analysis

CK Cheng, CT Ho, C Holtz, D Lee… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
As technology nodes continue to advance relentlessly, geometric pitch scaling starts to slow
down. In order to retain the trend of Moore's law, design technology co-optimization (DTCO) …

Data-driven multi-objective optimization with neural network-based sensitivity analysis for semiconductor devices

MH Oh, K Lee, S Kim, BG Park - Engineering Applications of Artificial …, 2023 - Elsevier
Statistical modeling and optimization are critical for product quality management and
technology development in the manufacturing industry. As the emerging device appears and …