Underfill flow in flip-chip encapsulation process: a review
The scope of review of this paper focused on the precuring underfilling flow stage of
encapsulation process. A total of 80 related works has been reviewed and being classified …
encapsulation process. A total of 80 related works has been reviewed and being classified …
Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review
YJ Jang, A Sharma, JP Jung - Materials, 2023 - mdpi.com
Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …
Regional segregation with spatial considerations-based analytical filling time model for non-Newtonian power-law underfill fluid in flip-chip encapsulation
This paper presents a new analytical filling time model to predict the flow of non-Newtonian
underfill fluid during flip-chip encapsulation process. The current model is formulated based …
underfill fluid during flip-chip encapsulation process. The current model is formulated based …
[HTML][HTML] Impact of TSV bump and redistribution layer on crosstalk delay and power loss
The performance of a 3D IC is primarily reliant on the selection of an appropriate bump
shape. The most prevalent bump shape (cylindrical) is experiencing substantial stress …
shape. The most prevalent bump shape (cylindrical) is experiencing substantial stress …
Filling efficiency of flip-chip underfill encapsulation process
Purpose This paper aims to introduce a new indicative parameter of filling efficiency to
quantify the performance and productivity of the flip-chip underfill encapsulation process …
quantify the performance and productivity of the flip-chip underfill encapsulation process …
Underfill material property dependence of lifetime and mechanical behavior of BGA package: EBSD and FEM investigations
D Kim, J Park, J Jang, H Yang, K Kim, C Oh… - Microelectronics …, 2023 - Elsevier
This study experimentally and numerically investigated the endurance life and mechanical
behavior of the ball grid array (BGA) packages according to the presence of underfill and the …
behavior of the ball grid array (BGA) packages according to the presence of underfill and the …
Effect of introducing high temperature gradients on IMC growth and shear properties in hourglass-shaped microbump joints during thermocompression bonding
C Tang, Z Chen, W Zhu - Journal of Materials Science: Materials in …, 2023 - Springer
Hourglass-shaped microbump joints are expected to be used in three-dimensional (3D) chip
stacking interconnect technology due to their strong resistance to electromigration and great …
stacking interconnect technology due to their strong resistance to electromigration and great …
A novel analytical filling time chart for design optimization of flip-chip underfill encapsulation process
Underfill encapsulation process regularly encounters productivity issue of long filling time
that incurs additional manufacturing costs. The package was optimized to attain least filling …
that incurs additional manufacturing costs. The package was optimized to attain least filling …
Performance analysis of bump in tapered tsv: impact on crosstalk and power loss
This study addresses the first feasible, and comprehensive approach to demonstrate a
compact resistance-inductance-capacitance-conductance (RLCG) model for a multi-walled …
compact resistance-inductance-capacitance-conductance (RLCG) model for a multi-walled …
[HTML][HTML] Flip-chip package solder-underfill reliability using finite element analysis
NREG Lim, AT Ubando, JA Gonzaga - Results in Engineering, 2024 - Elsevier
A semiconductor package is responsible to safeguard the die from the external environment
that can affect its performance and reliability. A flip-chip package ensures that the assembly …
that can affect its performance and reliability. A flip-chip package ensures that the assembly …