Unveiled Ferroelectricity in Well‐Known Non‐Ferroelectric Materials and Their Semiconductor Applications
Ferroelectric materials are considered ideal for emerging memory devices owing to their
characteristic remanent polarization, which can be switched by applying a sufficient electric …
characteristic remanent polarization, which can be switched by applying a sufficient electric …
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry
Future product applications demand increasing performance with reduced power
consumption, which motivates the pursuit of high-performance at reduced operating …
consumption, which motivates the pursuit of high-performance at reduced operating …
A 14 nm FinFET 128 Mb SRAM With V Enhancement Techniques for Low-Power Applications
Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A
0.064 μ m ^2 and a 0.080 μ m ^2 6T SRAM bitcells are designed for high-density (HD) and …
0.064 μ m ^2 and a 0.080 μ m ^2 6T SRAM bitcells are designed for high-density (HD) and …
Comprehensive study of security and privacy of emerging non-volatile memories
Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-
transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and …
transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and …
A 16 nm 128 Mb SRAM in High- Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications
YH Chen, WM Chan, WC Wu, HJ Liao… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
A 128 Mb 0.07 μm 2 6T high-density SRAM bitcell with write-assist circuitry has been
successfully implemented using 16 nm high-k metal gate FinFET technology. This study …
successfully implemented using 16 nm high-k metal gate FinFET technology. This study …
Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS
The conventional six-transistor static random access memory (SRAM) cell allows high
density and fast differential sensing but suffers from half-select and read-disturb issues …
density and fast differential sensing but suffers from half-select and read-disturb issues …
A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications
J Chang, YH Chen, WM Chan, SP Singh… - … Solid-State Circuits …, 2017 - ieeexplore.ieee.org
The growing demand for battery powered mobile devices is a major driver for reducing
power and continued area scaling in SOC chips. Continued scaling of the transistor and …
power and continued area scaling in SOC chips. Continued scaling of the transistor and …
A 23.6-Mb/mm SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications
Z Guo, D Kim, S Nalam, J Wiedemer… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A 23.6-Mb/mm 2 and a 20.4-Mb/mm 2 SRAM arrays are manufactured in a 10-nm FinFET
CMOS technology, utilizing high-density 0.0312 μm 2 and low-voltage 0.0367 μm 2 6T …
CMOS technology, utilizing high-density 0.0312 μm 2 and low-voltage 0.0367 μm 2 6T …
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies
In this paper, a 7T SRAM cell with differential write and single ended read operations
working in the near-threshold region is proposed. The structure is based on modifying a …
working in the near-threshold region is proposed. The structure is based on modifying a …