Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration

H Genc, S Kim, A Amid, A Haj-Ali, V Iyer… - 2021 58th ACM/IEEE …, 2021 - ieeexplore.ieee.org
DNN accelerators are often developed and evaluated in isolation without considering the
cross-stack, system-level effects in real-world environments. This makes it difficult to …

Compute-in-memory technologies and architectures for deep learning workloads

M Ali, S Roy, U Saxena, T Sharma… - … Transactions on Very …, 2022 - ieeexplore.ieee.org
The use of deep learning (DL) to real-world applications, such as computer vision, speech
recognition, and robotics, has become ubiquitous. This can be largely attributed to a virtuous …

ARBiS: A hardware-efficient SRAM CIM CNN accelerator with cyclic-shift weight duplication and parasitic-capacitance charge sharing for ai edge application

C Zhao, J Fang, J Jiang, X Xue… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Computing-in-memory (CIM) relieves the Von Neumann bottleneck by storing the weights of
neural networks in memory arrays. However, two challenges still exist, hindering the efficient …

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory

S Lee, G Park, H Jeong - Sensors, 2023 - mdpi.com
This paper comparatively reviews sensing circuit designs for the most widely used
embedded memory, static random-access memory (SRAM). Many sensing circuits for SRAM …

Structured binary neural networks for image recognition

B Zhuang, C Shen, M Tan, P Chen, L Liu… - International Journal of …, 2022 - Springer
In this paper, we propose to train binarized convolutional neural networks (CNNs) that are of
significant importance for deploying deep learning to mobile devices with limited power …

An energy efficient computing-in-memory accelerator with 1T2R cell and fully analog processing for edge AI applications

K Zhou, C Zhao, J Fang, J Jiang, D Chen… - … on Circuits and …, 2021 - ieeexplore.ieee.org
In this work, a ReRAM-based energy-efficient CIM accelerator is presented with two
techniques for edge AI applications. Firstly, a circuit-algorithm co-design scheme is …

Energy-efficient XNOR-free in-memory BNN accelerator with input distribution regularization

H Kim, H Oh, JJ Kim - Proceedings of the 39th International Conference …, 2020 - dl.acm.org
SRAM-based in-memory Binary Neural Network (BNN) accelerators are garnering interests
as a platform for energy-efficient edge neural network computing thanks to their …

Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling

J Sun, P Houshmand, M Verhelst - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
In-Memory Computing (IMC) has emerged as a promising paradigm for energy-efficient,
throughput-efficient and area-efficient machine learning at the edge. However, the …

PATH: Evaluation of Boolean Logic Using Path-Based In-Memory Computing Systems

S Thijssen, MRH Rashed, SK Jha… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In-memory computing using nonvolatile memory is a promising pathway to accelerate data-
intensive applications. While substantial research efforts have been dedicated to executing …

HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads

S Negi, U Saxena, D Sharma, K Roy - arXiv preprint arXiv:2403.13577, 2024 - arxiv.org
Analog Compute-in-Memory (CiM) accelerators are increasingly recognized for their
efficiency in accelerating Deep Neural Networks (DNN). However, their dependence on …