Generation of new low-complexity march algorithms for optimum faults detection in SRAM

AZ Jidin, R Hussin, LW Fook, MS Mispan… - … on Computer-Aided …, 2022 - ieeexplore.ieee.org
Memory BIST implements March test techniques extensively for testing embedded memories
on a chip. A high-complexity test algorithm like the March MSS (18N) can guarantee the …

Modified March MSS for Unlinked Dynamic Faults Detection

LW Ying, R Hussin, N Ahmad… - 2022 IEEE 20th …, 2022 - ieeexplore.ieee.org
Dynamic faults detection is important in recent Random Access Memory (RAM)
technologies. However, there is less research performed to design memory test algorithms …

A March 5n FSM-Based Memory Built-In Self-Test (MBIST) Architecture with Diagnosis Capabilities

KH Ng, NE Alias, A Hamzah, MLP Tan… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
MBIST is a standard mechanism to test memory arrays and potentially detect all of the faults
that may be present inside the memory cells using an effective collection of algorithms …

Reduced March SR algorithm for deep-submicron SRAM testing

AZ Jidin, R Hussin, MS Mispan… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
Memory Built-In Self-Test (BIST) is a common method to test embedded memories on a chip
owing to its fast and low-cost testing. Its efficiency depends on the complexity and the fault …

A New Fail Address Memory Architecture for Cost-Effective ATE

H Lee, S Lee, S Kang - … Aided Design of Integrated Circuits and …, 2023 - ieeexplore.ieee.org
Memory test and repair has been generally applied to improve memory yield. However, due
to the high cost of automatic test equipment (ATE) equipment, which has been employed for …

[HTML][HTML] Memory Grouping for the Built-In Self-Test of Three-Dimensional Integrated Circuits

SY Huang, SH Huang - Electronics, 2024 - mdpi.com
As the complexity of circuit design continues to grow, the development of three-dimensional
(3D) integrated circuit (IC) technology has become increasingly vital. While 3D ICs offer …

A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing

J Lee, H Lee, S Lee, S Kang - IEEE Transactions on Very Large …, 2024 - ieeexplore.ieee.org
An algorithmic pattern generator (ALPG) has been developed within automatic test
equipment (ATE) due to the extensive number of test patterns required for testing the …

Implementation of minimized March SR algorithm in a memory BIST controller

AZ Jidin, R Hussin, MS Mispan, WF Lee… - Journal of Engineering …, 2022 - jet.utem.edu.my
Abstract Memory Built-In Self-Test (MBIST) is essential in testing memories on a chip. Its
efficiency depends on its fault coverage and the complexity of the algorithm used, which …

Testing nanometer memories: a review of architectures, applications, and challenges.

V Sontakke, D Atchina - International Journal of Electrical & …, 2024 - search.ebscohost.com
Newer defects in memories arising from shrinking manufacturing technologies demand
improved memory testing methodologies. The percentage of memories on chips continues …

A new 13N-complexity memory built-in self-test algorithm to balance static random access memory static fault coverage and test time.

AZ Jidin, R Hussin, MS Mispan… - International Journal of …, 2025 - search.ebscohost.com
As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip
manufacturing yield. There is a growing need to reduce the chip production time and cost …