This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit
supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover …

A novel multifunctional negative group delay circuit is proposed. The circuit can realize three
different negative group delay functions, including band-pass, high-pass and low-pass …

This paper presents an energy efficient full-duplex (FD) current-mode transceiver for on-chip
global interconnects. As it shares the same signaling port for transmitting and receiving …

This brief describes a synthesis of high-pass negative group delay (NGD) network
impedance. The fundamental expression of the high-pass NGD canonical transfer function is …

This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-
terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The …

Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal
processing systems, and this study aims to fill this gap. It presents a novel methodology for …

We demonstrate a 40-Gb/s PAM-4 transmitter having 2-tap pre-emphasis, whose power
consumption is significantly reduced by the use of toggling serializers. In addition, a new …

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-
chip (NoC) communication is demonstrated. The proposed MRI interface consists of …

We present a methodology for implementing NGD using a Finite Impulse Response (FIR)
filter. The NGD concept is counter-intuitive in nature, so we first provide the basic theory of …

The authors propose a hybrid transceiver and an energy‐efficient link architecture for
bidirectional multipoint‐to‐multipoint signalling across on‐chip global interconnect. The …