Tasks mapping in the network on a chip using an improved optimization algorithm

M Darbandi, AR Ramtin, OK Sharafi - International Journal of …, 2020 - emerald.com
Purpose A set of routers that are connected over communication channels can from network-
on-chip (NoC). High performance, scalability, modularity and the ability to parallel the …

Evaluation of multiple bit upset tolerant codes for NoCs buffering

F Silva, W Magalhães, J Silveira… - 2017 IEEE 8th Latin …, 2017 - ieeexplore.ieee.org
Newest technologies of integrated circuits manufacture allow billions of transistors arranged
in a single chip enabling to implement a complex parallel system, which requires a …

Subutai: Distributed synchronization primitives for legacy and novel parallel applications

RC Cataldo - 2019 - theses.hal.science
Parallel applications are essential for efficiently using the computational power of a
MultiProcessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale …

Analytical Performance Modeling of LECΔ Networkon-Chip Architecture

S Gautam, A Samad, M sarosh Umar - NeuroQuantology, 2022 - search.proquest.com
This paper targets the performance evaluation of different NoC based interconnection
networks which are essentially considered as a rational way to connect huge nodes of …

Multi-Objective Routing for Distributed Controllers

KY Rubin - 2021 - search.proquest.com
A long-term goal of future naval shipboard power systems is the ability to manage energy
flow with sufficient flexibility to accommodate future platform requirements such as better …