Overcoming the transimpedance limit: A tutorial on design of low-noise TIA

D Li, L Geng, F Maloberti… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Noise probably the single most important performance metric of the high-speed
transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The …

Experimental demonstration of a 160 Gbit/s 3D-integrated silicon photonics receiver with 1.2-pJ/bit power consumption

D Wu, D Wang, D Chen, J Yan, Z Dang, J Feng… - Optics …, 2023 - opg.optica.org
By using the flip-chip bonding technology, a high performances 3D-integrated silicon
photonics receiver is demonstrated. The receiver consists of a high-speed germanium …

Parallel Versus Serial: Design of an Optical Receiver With Integrated Blue Photodetectors and Digitally Tunable Low-End Cutoff Frequency for MicroLED-Based …

F Khoeini, B Pezeshki, E Afifi, A Tselikov… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article first analytically compares the energy efficiency of a serial optical link with a
parallel link with the same data throughput and bit error rate for interchip communication …

Application of Big Data Clustering Algorithm in Electrical Engineering Automation

Y Zhang, Z Zhang - Journal of Applied Mathematics, 2022 - Wiley Online Library
The existing control methods have the problem of imperfect automatic distribution linkage
model, which leads to excessive noise in the process of practical application. This paper …

A 40-Gb/s, 900-fJ/bit Dual-Channel Receiver in a 45-nm Monolithic RF/Photonic Integrated Circuit Process

G Movaghar, V Arrunategui, E Chansky… - IEEE Solid-State …, 2022 - ieeexplore.ieee.org
An energy-efficient dual-channel receiver (RX) for short-range optical interconnects is
integrated in a 45-nm RF/photonic process and characterized for electrical bandwidth to de …

4× 112 Gb/s hybrid integrated silicon receiver based on photonic-electronic co-design

Y Jin, Y Xie, Z Zhang, D Lu, M Yang, A Li… - Chinese Optics …, 2024 - opg.optica.org
A 4× 112 Gb/s hybrid-integrated optical receiver is demonstrated based on the silicon-
photonic vertical pin photodetector and silicon–germanium transimpedance amplifier. We …

A 50-Gb/s NRZ receiver targeting low-latency multi-chip module optical I/O in 45-nm SOI CMOS

Y Li, S Chen, Y Yang, Q Ma, M Zhong… - 2022 IEEE Asia …, 2022 - ieeexplore.ieee.org
This paper presents a 50-Gb/s optical receiver chipset in 45-nm silicon-on-insulator (SOI)
CMOS. It comprises a trans-impedance amplifier (TIA) cascaded by a clock and data …

A 128 Gbit/s 3D-integrated silicon photonics receiver with 1.5 pJ/bit power consumption

D Wu, D Wang, D Chen, J Yan, Z Dang… - 2022 Asia …, 2022 - ieeexplore.ieee.org
A 100 Gbit/s NRZ and 128 Gbit/s PAM-4 3D-integrated silicon photonics receiver with low
power consumption is reported. The receiver is implemented based on flip-chip 3D …

Energy Efficient Integrated Circuits and Systems for Communications and Sensing: RF to Optical

F Khoeini - 2022 - deepblue.lib.umich.edu
The trend of continually increasing demand for high-performance computation in artificial
intelligence, cloud computing, and virtual/augmented reality requires increasing chip-to-chip …