[PDF][PDF] Design and evaluation of cubic torus network-on-chip architecture
The network on chip is the key component of the achieving the high performance required
by the system designed on the single chip. The mesh and torus topologies have found there …
by the system designed on the single chip. The mesh and torus topologies have found there …
Comparative analysis of network‐on‐chip simulation tools
S Khan, S Anjum, UA Gulzari… - IET Computers & Digital …, 2018 - Wiley Online Library
Network‐on‐chip (NoC) is a reliable and scalable communication paradigm deemed as an
alternative to classic bus systems in modern systems‐on‐chip designs. Consequently, one …
alternative to classic bus systems in modern systems‐on‐chip designs. Consequently, one …
Bandwidth-constrained multi-objective segmented brute-force algorithm for efficient mapping of embedded applications on NoC architecture
Network-on-chip (NoC) is an emerging alternative to address the communication problem in
embedded system-on-chip designs. One of the key and major issues is the optimized …
embedded system-on-chip designs. One of the key and major issues is the optimized …
An efficient algorithm for mapping real time embedded applications on NoC architecture
Network-on-chip (NoC) has appeared to be an impending substitute for the communication
paradigm in modern very large scale integration embedded systems. Apart from many …
paradigm in modern very large scale integration embedded systems. Apart from many …
Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks
Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded
technologies. One of the main challenges of this system is its communication bottleneck …
technologies. One of the main challenges of this system is its communication bottleneck …
A network adaptive fault-tolerant routing algorithm for demanding latency and throughput applications of network-on-a-chip designs
Scalability is a significant issue in system-on-a-chip architectures because of the rapid
increase in numerous on-chip resources. Moreover, hybrid processing elements demand …
increase in numerous on-chip resources. Moreover, hybrid processing elements demand …
An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks
In this paper, we propose an optimized, search based near-optimal mapping heuristic,
named as ONMAP for mapping real time embedded application workloads on 2D based on …
named as ONMAP for mapping real time embedded application workloads on 2D based on …
A low latency and low power indirect topology for on-chip communication
This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology
for on-chip communication. Main aspects of this work are the description of the architectural …
for on-chip communication. Main aspects of this work are the description of the architectural …
A horizontal fat mesh interconnection network
The mesh interconnection network is the most popular topology for the network on chip
architecture. The horizontal fat mesh topology is designed to keep all the advantages of the …
architecture. The horizontal fat mesh topology is designed to keep all the advantages of the …
[PDF][PDF] On Performance of Modified Torus Interconnection Networks
Parallel processing systems are the most powerful tools to real time applications that
requires large processing of data. In recent years of advancement within the technology, a …
requires large processing of data. In recent years of advancement within the technology, a …