Exploiting input data sparsity in neural network compute units
DH Woo, R Narayanaswami - US Patent 9,818,059, 2017 - Google Patents
(57) ABSTRACT A computer-implemented method includes receiving, by a computing
device, input activations and determining, by a controller of the computing device, whether …
device, input activations and determining, by a controller of the computing device, whether …
Determining orders of execution of a neural network
W Craddock, F Viger - US Patent 10,699,186, 2020 - Google Patents
Abstract Systems and methods are provided for determining an order of execution of a
neural network. For instance, data indicative of a neural network and data indicative of an …
neural network. For instance, data indicative of a neural network and data indicative of an …
Control flow in a thread-based environment without branching
M Alsup, Y Jiao, B Beylin, M Lukyanov… - US Patent …, 2017 - Google Patents
A method for computing in a thread-based environment provides manipulating an execution
mask to enable and disable threads when executing multiple conditional function clauses for …
mask to enable and disable threads when executing multiple conditional function clauses for …
Exploiting input data sparsity in neural network compute units
DH Woo, R Narayanaswami - US Patent 10,360,163, 2019 - Google Patents
A computer-implemented method includes receiving, by a computing device, input
activations and determining, by a controller of the computing device, whether each of the …
activations and determining, by a controller of the computing device, whether each of the …
Method and apparatus for efficient execution of nested branches on a graphics processor unit
WY Chen, GY Lueh, S Maiyuran - US Patent 9,766,892, 2017 - Google Patents
US9766892B2 - Method and apparatus for efficient execution of nested branches on a graphics
processor unit - Google Patents US9766892B2 - Method and apparatus for efficient execution …
processor unit - Google Patents US9766892B2 - Method and apparatus for efficient execution …
Memory management in virtualized computing
X Zhang, XU Dongxiao - US Patent App. 14/778,054, 2016 - Google Patents
BACKGROUND 0002 The background description provided herein is for the purpose of
generally presenting the context of the disclo sure. Unless otherwise indicated herein, the …
generally presenting the context of the disclo sure. Unless otherwise indicated herein, the …
Control flow mechanism for execution of graphics processor instructions using active channel packing
SM Maiyuran, GY Lueh, S Pal, G Chen… - US Patent …, 2021 - Google Patents
An apparatus to facilitate control flow in a graphics processing system is disclosed. The
apparatus includes logic a plurality of execution units to execute single instruction, multiple …
apparatus includes logic a plurality of execution units to execute single instruction, multiple …
Dynamic thread splitting having multiple instruction pointers for the same thread
HC Nalluri, S Pal, S Maiyuran, J Chandra - US Patent 10,789,071, 2020 - Google Patents
Abstract Systems, apparatuses and methods may provide for associating a first instruction
pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread …
pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread …
Trace-based instruction execution processing
M Alsup, B Beylin, M Shebanow, S Park - US Patent 9,483,264, 2016 - Google Patents
(57) ABSTRACT A method for executing instructions in a thread processing environment
includes determining a multiple requirements that must be satisfied and resources that must …
includes determining a multiple requirements that must be satisfied and resources that must …
Simd channel utilization under divergent control flow
G Chen, PJ Ashar, S Maiyuran… - US Patent App. 15 …, 2018 - Google Patents
Methods and apparatus relating to techniques for improved SIMD channel utilization in a
divergent control flow environment. In an example, an apparatus comprises logic, at least …
divergent control flow environment. In an example, an apparatus comprises logic, at least …