A 270-mV 6T SRAM Using Row-Based Dual-Phase V DD Control in 28-nm CMOS

A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications

M Karamimanesh, E Abiri, K Hassanli… - … -International Journal of …, 2022 - Elsevier
In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to
reducing power and energy consumption can show high reliability and have the least error …
被引用次数：20 相关文章

Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells

YV Narayana, P VVKDV - Sustainable Computing: Informatics and …, 2022 - Elsevier
For many decades, SRAM cell design with low power dissipation is the problem of interest
for researchers due to its numerous applications in embedded systems. In this research …
被引用次数：6 相关文章 所有 2 个版本

A novel low-energy half-select-free 9T SRAM cell based on CNTFETs with enhanced write performance

SHH Nemati, N Eslami, MH Moaiyeri - AEU-International Journal of …, 2025 - Elsevier
This work proposes a novel 9 T SRAM cell based on carbon nanotube field-effect transistors
(CNTFETs). The design features an innovative writing technique, leveraging a floating …
相关文章

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

JS Wang, CT Liu, YC Hou - IEEE Journal of Solid-State Circuits, 2025 - ieeexplore.ieee.org
Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate
read-and-write assist circuits sacrifice access speed too much, leading to poor energy …
相关文章

Schmitt-Trigger-Based Low Power SRAM Implemented Using 45-nm CMOS Technology

RB Oruga, CVD Dimalibot, JMD Matibag… - 2023 IEEE Region …, 2023 - ieeexplore.ieee.org
This paper presents a Schmitt-trigger-based SRAM with a separated read port, which
significantly improves read static noise margin (RSNM) and consumes low energy. Post …
相关文章