This paper presents an overview of a comprehensive collection of on-line testing techniques
for VLSI. Such techniques are for instance: self-checking design, allowing high quality …

Totally self-checking (TSC) Berger code checker designs are presented. The generalized
Berger check partitioning is derived. It is proven that a TSC Berger code checker can be …

Delay-insensitive (unordered) codes have been used to encode data in various
asynchronous systems such as asynchronous circuits and buses. In this paper, a new …

Reliable floating-point arithmetic is vital for dependable computing systems. It is also
important for future high-density VLSI realizations that are vulnerable to soft-errors …

One of several approaches for designing highly-reliable systems relies on using error
detecting codes (EDCs) and implementing digital circuits as self-checking. One class of …

This survey introduces the design concepts of self-checking circuits and discusses research
activities in on-line hardware-checking techniques developed in Eastern Europe, including …

This paper tackles the open problem of designing combinational self-testing checkers
(STCs) for K-pair 2-rail codes which are self-testing, even by a subset of codewords, such …

A technique for designing efficient checkers for conventional Berger code is proposed in this
paper. The check bits are derived by partitioning the information bits into two blocks, and …

Several schemes for designing encoders and self-testing checkers (STCs) for systematic
unidirectional error detecting (UED) codes are known. In this paper, we propose the new …

Paschalis et al.(1988) have given a structured method to design TSC m-out-of-2m code
checkers suitable for VLSI implementation. In this correspondence we give sufficient …