A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon

C Convertino, CB Zota, H Schmid, D Caimi… - nature …, 2021 - nature.com
Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike
conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less …

Sub-10-nm diameter vertical nanowire p-type GaSb/InAsSb tunnel FETs

Y Shao, JA del Alamo - IEEE electron device letters, 2022 - ieeexplore.ieee.org
In this letter, we report the realization of sub-10-nm diameter vertical nanowire (VNW) p-type
tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top …

High Current Density Vertical Nanowire TFETs with I60>1μA/μm

G Rangasamy, Z Zhu, LE Wernersson - IEEE Access, 2023 - ieeexplore.ieee.org
We present experimental data for a vertical, 22-nm-diameter InAs/(In) GaAsSb nanowire
Tunnel Field-Effect Transistor that exhibits the highest reported I60 of, paving the way for low …

Steep slope carbon nanotube tunneling field-effect transistor

CS Pang, SJ Han, Z Chen - Carbon, 2021 - Elsevier
Tunneling field-effect transistors (TFETs) have emerged as a potential candidate to
outperform conventional metal-oxide-semiconductor FETs at low voltages, since their …

A novel high-performance planar InAs/GaSb face-tunneling FET with implanted drain for leakage current reduction

Z Lyu, H Lv, Y Zhang, Y Zhang, Y Zhu… - … on Electron Devices, 2021 - ieeexplore.ieee.org
In this article, a novel planar InAs/GaSb heterojunction face-tunneling FET (HFTFET) is
proposed for device performance improvement. As is known in previous studies, the entire …

III-V-on-Si transistor technologies: Performance boosters and integration

D Caimi, H Schmid, T Morf, P Mueller, M Sousa… - Solid-State …, 2021 - Elsevier
In this work, we review progress in III-V transistor technologies. Key approaches for silicon
integration are described, with a distinction being made between large area layer transfer …

A multiscale simulation framework for steep-slope Si nanowire cold source FET

W Gan, K Luo, G Qi, RJ Prentki, F Liu… - … on Electron Devices, 2021 - ieeexplore.ieee.org
Source engineering is an emerging technique to achieve steep-slope switching FET. To
bridge the new carrier filtering mechanism and device performance, a multiscale simulation …

gm/I d g_m/I_d Analysis of vertical nanowire III–V TFETs

G Rangasamy, Z Zhu, LO Fhager… - Electronics …, 2023 - Wiley Online Library
Experimental data on analog performance of gate‐all‐around III‐V vertical Tunnel Field‐
Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal …

TFET Circuit Configurations Operating below 60 mV/dec

G Rangasamy, Z Zhu, LO Fhager… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Tunnel Field-Effect Transistors (TFETs) offer more energy efficient alternative to CMOS for
design of low power circuits. In spite of this potential, circuits based on TFETs have not been …

Source Design of Vertical III-V Nanowire Tunnel Field-Effect Transistors

G Rangasamy, Z Zhu… - IEEE Journal on …, 2024 - ieeexplore.ieee.org
We systematically fabricate devices and analyze data for vertical InAs/(In) GaAsSb nanowire
tunnel field-effect transistors (TFETs), to study the influence of source dopant position and …