Statistical timing analysis: From basic principles to state of the art
D Blaauw, K Chopra, A Srivastava… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
Static-timing analysis (STA) has been one of the most pervasive and successful analysis
engines in the design of digital circuits for the last 20 years. However, in recent years, the …
engines in the design of digital circuits for the last 20 years. However, in recent years, the …
Statistical timing analysis for intra-die process variations with spatial correlations
A Agarwal, D Blaauw, V Zolotov - ICCAD-2003. International …, 2003 - ieeexplore.ieee.org
Process variations have become a critical issue in performance verification of high-
performance designs. We present a new, statistical timing analysis method that accounts for …
performance designs. We present a new, statistical timing analysis method that accounts for …
Statistical static timing analysis: A survey
C Forzan, D Pandini - Integration, 2009 - Elsevier
As the device and interconnect physical dimensions decrease steadily in modern nanometer
silicon technologies, the ability to control the process and environmental variations is …
silicon technologies, the ability to control the process and environmental variations is …
[图书][B] Statistical analysis and optimization for VLSI: Timing and power
Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …
Statistical timing analysis under spatial correlations
H Chang, SS Sapatnekar - IEEE Transactions on Computer …, 2005 - ieeexplore.ieee.org
Process variations are of increasing concern in today's technologies, and they can
significantly affect circuit performance. An efficient statistical timing analysis algorithm that …
significantly affect circuit performance. An efficient statistical timing analysis algorithm that …
Understanding the effect of process variations on the delay of static and domino logic
In this paper, the effect of process variations on delay is analyzed in depth for both static and
dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay …
dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay …
On monadic NP vs monadic co-NP
It is a well-known result of Fagin that the complexity class NP coincides with the class of
problems expressible in existential second-order logic (Σ11). Monadic NP is the class of …
problems expressible in existential second-order logic (Σ11). Monadic NP is the class of …
Layout-aware switching activity localization to enhance hardware Trojan detection
H Salmani, M Tehranipoor - IEEE Transactions on Information …, 2011 - ieeexplore.ieee.org
Government agencies and the semiconductor industry have raised serious concerns about
malicious modifications to the integrated circuits. The added functionality known as …
malicious modifications to the integrated circuits. The added functionality known as …
Semi-supervised low-rank mapping learning for multi-label classification
Multi-label problems arise in various domains including automatic multimedia data
categorization, and have generated significant interest in computer vision and machine …
categorization, and have generated significant interest in computer vision and machine …
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Recent study shows that the existing first order canonical timing model is not sufficient to
represent the dependency of the gate delay on the variation sources when processing and …
represent the dependency of the gate delay on the variation sources when processing and …