Designing fast fourier transform accelerators for orthogonal frequency-division multiplexing systems
Designing accelerators for the real-time computation of Fast Fourier Transform (FFT)
algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) …
algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) …
Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platform
In this paper, we present the mapping of Radix-2 and Radix-4 FFT algorithms using CREMA,
a Coarse-Grain Reconfigurable Array (CGRA) with mapping adaptiveness. CREMA is …
a Coarse-Grain Reconfigurable Array (CGRA) with mapping adaptiveness. CREMA is …
Effects of scaling a coarse-grain reconfigurable array on power and energy consumption
In recent past, we scaled a 4× 8 processing element (PE) template-based Coarse-Grain
Reconfigurable Array (CGRA) to a 4× 4, 4× 16 and 4× 32 PE CGRA and generated matrix …
Reconfigurable Array (CGRA) to a 4× 4, 4× 16 and 4× 32 PE CGRA and generated matrix …
HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms
This paper presents design, development and evaluation of an eXtra-large Scale,
Homogeneous and a Heterogeneous Accelerator-Rich Platform (HARP 2) for massively …
Homogeneous and a Heterogeneous Accelerator-Rich Platform (HARP 2) for massively …
A reconfigurable application-specific instruction-set processor for fast fourier transform processing
W Hussain, X Chen, G Ascheid… - 2013 IEEE 24th …, 2013 - ieeexplore.ieee.org
In this paper, we have presented a Reconfigurable Application-specific Instruction-set
Processor (rASIP) that processes mixed-radix (2, 4) 64 and 128-point Fast Fourier Transform …
Processor (rASIP) that processes mixed-radix (2, 4) 64 and 128-point Fast Fourier Transform …
Exploiting control management to accelerate radix-4 fft on a reconfigurable platform
In this paper, we present the mapping of 64 and 1024-point FFT algorithms on a Radix-4
FFT accelerator generated using a hardware template called CREMA. The accelerator …
FFT accelerator generated using a hardware template called CREMA. The accelerator …
Implementation of IEEE-802.11 a/g receiver blocks on a coarse-grained reconfigurable array
This paper presents the implementation of Orthogonal Frequency-Division Multiplexing
receiver blocks as accelerators using a template-based Coarse-Grained Reconfigurable …
receiver blocks as accelerators using a template-based Coarse-Grained Reconfigurable …
Adaptive neural acceleration unit based on heterogeneous multicore hardware architecture FPGA and software-defined hardware
SF Su, MW Chang - Journal of the Chinese Institute of Engineers, 2024 - Taylor & Francis
This study is anchored in a heterogeneous multicore hardware architecture, specifically
Field Programmable Gate Arrays (FPGAs), and software-defined hardware. It employs …
Field Programmable Gate Arrays (FPGAs), and software-defined hardware. It employs …
Power mitigation by performance equalization in a heterogeneous reconfigurable multicore architecture
This paper presents an integrated self-aware computing model mitigating the power
dissipation of a heterogeneous reconfigurable multicore architecture by dynamically scaling …
dissipation of a heterogeneous reconfigurable multicore architecture by dynamically scaling …
Design and evaluation of correlation accelerator in IEEE-802.11 a/g receiver using a template-based coarse-grained reconfigurable array
This paper presents the design and evaluation of a large scale template-based Coarse-
Grained Reconfigurable Array (CGRA) generated accelerator that processes correlation …
Grained Reconfigurable Array (CGRA) generated accelerator that processes correlation …