Nanowire electronics: from nanoscale to macroscale

C Jia, Z Lin, Y Huang, X Duan - Chemical reviews, 2019 - ACS Publications
Semiconductor nanowires have attracted extensive interest as one of the best-defined
classes of nanoscale building blocks for the bottom-up assembly of functional electronic and …

Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits

A Afifi, A Ayatollahi, F Raissi - 2009 European Conference on …, 2009 - ieeexplore.ieee.org
Memristor nanodevices have good properties for use as synapses to add dynamic learning
to neuromorphic networks implemented in crossbar-based CMOS/Nano hybrids. In this …

A survey of fault-tolerance algorithms for reconfigurable nano-crossbar arrays

O Tunali, M Altun - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
Nano-crossbar arrays have emerged as a promising and viable technology to improve
computing performance of electronic circuits beyond the limits of current CMOS. Arrays offer …

[PDF][PDF] Faster optimal single-row placement with fixed ordering

U Brenner, J Vygen - Proceedings of the conference on Design …, 2000 - dl.acm.org
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{ku vwu& ku& vvpd kv v u&xevnoQ vwu u" u (y u&vw) uD hv u ed hlfx {&v x {y" kuA u& eut …

Towards logic functions as the device

P Shabadi, A Khitun, P Narayanan… - 2010 IEEE/ACM …, 2010 - ieeexplore.ieee.org
This paper argues for alternate state variables and new types of sophisticated devices that
implement more functionality in one computational step than typical devices based on …

CMOS control enabled single-type FET NASIC

P Narayanan, M Leuchtenburg… - 2008 IEEE Computer …, 2008 - ieeexplore.ieee.org
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of
Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS …

Heterogeneous Two-Level logic and its density and fault tolerance implications in nanoscale fabrics

T Wang, P Narayanan, CA Moritz - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Most proposed nanoscale computing architectures are based on a certain type of two-level
logic family, eg, and–or, nor–nor, nand–nand, etc. In this paper, a new fabric architecture …

Spin wave functions nanofabric update

P Shabadi, A Khitun, K Wong, PK Amiri… - 2011 IEEE/ACM …, 2011 - ieeexplore.ieee.org
We provide a comprehensive progress update on the magnonic spin wave functions
nanofabric. Spin wave propagation does not involve any physical movement of charge …

Design of spin wave functions-based logic circuits

P Shabadi, SN Rajapandian, S Khasanvis, CA Moritz - Spin, 2012 - World Scientific
Over the past few years, several novel nanoscale computing concepts have been proposed
as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In …

Building hierarchical switch network using openflow

H Shimonishi, H Ochiai, N Enomoto… - 2009 International …, 2009 - ieeexplore.ieee.org
No single layers and technologies can construct a large scale network, thus networks are
organized as a physical structure of variety of layers. For example in data center, networks …