A 3-dimensional array of NOR memory strings being organized by planes of NOR memory
strings, in which (i) the storage transistors in the NOR memory strings situated in a first group …

Some embodiments include a memory array having rows of fins. Each fin has at least one
channel region. Each channel region extends from a first source/drain region to a second …

Methods, systems, and devices for transistor configurations for vertical memory arrays are
described. A memory device may implement a multi-transistor architecture, such as a two …

(57) ABSTRACT A process includes (a) providing a semiconductor substrate having a
planar surface;(b) forming a plurality of thin-film layers above the planar surface of the …

A process includes (a) providing a semiconductor substrate having a planar surface;(b)
forming a plurality of thin-film layers above the planar surface of the semiconductor …

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory
strings, in which (i) the storage transistors in the NOR memory strings situated in a first group …

A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit
formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non …

A thin-film storage transistor formed in a memory array above a planar surface of a
semiconductor substrate, includes (a) first and second planar dielectric layers, each being …

A process for building a 3-Dimensional NOR memory array avoids the challenge of etching
a conductor material that is aimed at providing local word lines at a fine pitch. The process …

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three
dimensional stacks of active strips. Each active strip includes a shared source sublayer and …