We review the state-of-the-art in the understanding of planar NAND Flash memory reliability
and discuss how the recent move to three-dimensional (3D) devices has affected this field …

In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND
Flash arrays. The main features of such arrays resulting from their mainstream integration …

Three-dimensional (3D) semicircular split-gate flash memory cells have been successfully
developed for the first time. Reduction of fringing field effects is essential to extract maximum …

With the evolution of semiconducting industries, thermomechanical failure induced in a
multilayered structure with a high aspect ratio during manufacturing and operation has …

Abstract We analyzed Incremental Step Pulse Programming (ISPP) slope degradation to
improve the program efficiency of 3D NAND Flash memory using both measurement and …

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-
D NAND Flash technologies. Experimental results on memory arrays reveal an increase of …

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely
accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability …

We illustrate novel optimization techniques via simulations for Hopfield networks constructed
from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic …

The effects of taper angle of the string and the number of layers on the electrical
characteristics of vertical NAND flash memories are investigated. Simulation results show …

We present a semianalytical model for the electrostatics and the current-voltage
characteristics of Macaroni MOSFETs based on the exact solution of the Poisson equation …