A survey of architectural approaches for data compression in cache and main memory systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …

Chip multithreading: Opportunities and challenges

L Spracklen, SG Abraham - 11th International symposium on …, 2005 - ieeexplore.ieee.org
Chip multi-threaded (CMT) processors provide support for many simultaneous hardware
threads of execution in various ways, including simultaneous multithreading (SMT) and chip …

DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

Base-delta-immediate compression: Practical data compression for on-chip caches

G Pekhimenko, V Seshadri, O Mutlu… - Proceedings of the 21st …, 2012 - dl.acm.org
Cache compression is a promising technique to increase on-chip cache capacity and to
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …

Review and evaluation of commonly-implemented background subtraction algorithms

Y Benezeth, PM Jodoin, B Emile… - 2008 19th …, 2008 - ieeexplore.ieee.org
Locating moving objects in a video sequence is the first step of many computer vision
applications. Among the various motion-detection techniques, background subtraction …

[PDF][PDF] Research problems and opportunities in memory systems

O Mutlu, L Subramanian - Supercomputing frontiers and …, 2014 - superfri.susu.ru
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

Frequent pattern compression: A significance-based compression scheme for L2 caches

A Alameldeen, D Wood - 2004 - minds.wisconsin.edu
With the widening gap between processor and memory speeds, memory system designers
may find cache compression beneficial to increase cache capacity and reduce off-chip …

Scaling the bandwidth wall: challenges in and avenues for CMP scaling

BM Rogers, A Krishna, GB Bell, K Vu, X Jiang… - Proceedings of the 36th …, 2009 - dl.acm.org
As transistor density continues to grow at an exponential rate in accordance to Moore's law,
the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-chip …

What your DRAM power models are not telling you: Lessons from a detailed experimental study

S Ghose, AG Yaglikçi, R Gupta, D Lee… - Proceedings of the …, 2018 - dl.acm.org
Main memory (DRAM) consumes as much as half of the total system power in a computer
today, due to the increasing demand for memory capacity and bandwidth. There is a …

More on average case vs approximation complexity

M Alekhnovich - 44th Annual IEEE Symposium on Foundations …, 2003 - ieeexplore.ieee.org
We consider the problem to determine the maximal number of satisfiable equations in a
linear system chosen at random. We make several plausible conjectures about the average …