Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …

Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density
alternative to SRAM for large on-chip caches. However, its high write energy has been …

This paper evaluates the viability of user-level software management of a hybrid
DRAM/NVM main memory system. We propose an operating system (OS) and programming …

Recently, researchers have explored way-based hybrid SRAM-NVM (non-volatile memory)
last level caches (LLCs) to bring the best of SRAM and NVM together. However, the limited …

Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because
of its attractive features such as high storage density and ultra low leakage power. However …

This paper presents a novel concept called write intensity prediction for energy-efficient non-
volatile caches as well as the architecture that implements the concept. The key idea is to …

Use of non-volatile memory (NVM) devices such as resistive RAM (ReRAM) and spin
transfer torque RAM (STT-RAM) for designing on-chip caches holds the promise of providing …

DRAM consumes significant static energy both in active and idle state due to continuous
leakage and refresh power. Various byte-addressable non-volatile memory (NVM) …

Spin-Transfer Torque RAM (STT-RAM), a promising alternative to SRAM for reducing
leakage power consumption, has been widely studied to mitigate the impact of its …

This article proposes Benzene, an energy-efficient distributed SRAM/STT-RAM hybrid cache
for manycore systems running multiple applications. It is based on the observation that a …