Neuromorphic computing using NAND flash memory architecture with pulse width modulation scheme
A novel operation scheme is proposed for high-density and highly robust neuromorphic
computing based on NAND flash memory architecture. Analog input is represented with time …
computing based on NAND flash memory architecture. Analog input is represented with time …
Low-power binary neuron circuit with adjustable threshold for binary neural networks using NAND flash memory
Recent studies have demonstrated that binary neural networks (BNN) could achieve a
satisfying inference accuracy on representative image datasets. BNN conducts XNOR and …
satisfying inference accuracy on representative image datasets. BNN conducts XNOR and …
A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities
Z Chen, T Ohsawa - IEICE Transactions on Electronics, 2022 - search.ieice.org
A new software based in-situ training (SBIST) method to achieve high accuracies is
proposed for binarized neural networks inference accelerator chips in which measured …
proposed for binarized neural networks inference accelerator chips in which measured …
Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm
In recent years, deep neural network (DNN) has achieved considerable results on many
artificial intelligence tasks, eg natural language processing. However, the computation …
artificial intelligence tasks, eg natural language processing. However, the computation …