Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

BNK Reddy - Analog integrated circuits and signal processing, 2020 - Springer
Now a days, an efficient arithmetic operations are important to accomplish the high
performance. In every one of these applications, multiplier is an important arithmetic …

Fast signed multiplier using Vedic Nikhilam algorithm

SR Sahu, BK Bhoi, M Pradhan - IET Circuits, Devices & …, 2020 - Wiley Online Library
Vedic algorithm is beneficial for the application in the design of high‐speed computing and
hardware. This study presents a fast signed binary multiplication structure based on Vedic …

Design and implementation of Novel 32-bit MAC unit for DSP applications

HM Rakesh, GS Sunitha - 2020 International Conference for …, 2020 - ieeexplore.ieee.org
In today's smart and fast computing world, the designing of high speed and low energy
consumption based Digital Signal Processors (DSPs) is a realistic and ever embryonic area …

Time efficient signed Vedic multiplier using redundant binary representation

RK Barik, M Pradhan, R Panda - The Journal of Engineering, 2017 - Wiley Online Library
This study presents a high‐speed signed Vedic multiplier (SVM) architecture using
redundant binary (RB) representation in Urdhva Tiryagbhyam (UT) sutra. This is the first ever …

An FPGA and ASIC Implementation of Cubing Architecture

BNK Reddy, B Seetharamulu, GS Krishna… - Wireless Personal …, 2022 - Springer
The optimization of VLSI design is playing an important role in the development of
technological applications. The optimization of VLSI technology helps to increase the …

Square root for perfect square numbers using vedic mathematics

SR Savarimuthu, KC Muthuraji… - AIP conference …, 2023 - pubs.aip.org
In modern systems, the square root of a number is calculated using the long division
method. The radical can be calculated using several diverse approaches. This study focuses …

Analysis of Delay in 16× 16 Signed Binary Multiplier

N Behera, M Pradhan, PK Mishro - Proceedings of the International …, 2023 - Springer
In a digital verification system, multipliers play a crucial role. In practice, multipliers are
grouped in to unsigned and signed types. An unsigned multiplier performs the multiplication …

FPGA implementation of square and cube architecture using vedic mathematics

S Barve, S Raveendran, C Korde… - … on Smart Electronic …, 2018 - ieeexplore.ieee.org
Squaring and cubing units have importance in various applications in digital signal
processing. This paper proposes new squaring architectures based on vedic mathematics …

Developing high-performance AVM based VLSI computing systems: a study

SK Panda, DC Panda - Progress in Computing, Analytics and Networking …, 2018 - Springer
With the initiation of ancient Vedic mathematics (AVM) concepts, very large-scale integration
technique becomes more powerful in developing various VLSI computing systems. In the …

Efficient hardware implementation of cube architecture using Yavadunam Sutra on FPGA

M Thakare, P Yash, D Chakraborty… - 2021 IEEE international …, 2021 - ieeexplore.ieee.org
Modern computational devices are in need of efficient and optimized hardware architectures
with low power and reduced computational complexity. This work presents an efficient and …