Heuristic Analysis of Multiplierless Desensitized Half-Band Decimation Filter for Wireless Applications
A Abinaya, M Maheswari - Journal of Circuits, Systems and …, 2022 - World Scientific
This paper elucidates the half-band FIR filter, which plays an important role when applying
decimation by a factor of two. When the down-conversion is applied in sampling rate, this …
decimation by a factor of two. When the down-conversion is applied in sampling rate, this …
Adjustable Nyquist-rate system for single-bit sigma-delta ADC with alternative FIR architecture
V Frick, F Dadouche, H Berviller - International Journal of …, 2016 - Taylor & Francis
This paper presents a new smart and compact system dedicated to control the output
sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma …
sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma …
A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator
J Lee, S Song, J Roh - International Journal of Electronics, 2020 - Taylor & Francis
This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator
(DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) …
(DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) …
Data filtering and machine learning in frequency converter-driven pump process identification
A Simola - 2020 - lutpub.lut.fi
Pumps consume roughly a fifth of the total energy consumed by electrical motors in the
world. There exists a huge potential in pump systems for energy savings and increases in …
world. There exists a huge potential in pump systems for energy savings and increases in …
A 7.3 μW decimation filter for 15 bit 25 kHz audio ΣΔ modulator
This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to
Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter …
Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter …
Optimization Techniques for Throughput Enhancement in FPGA Specific Designs
HMAD Kamboh - 2014 - repository.pastic.gov.pk
The prime goal of design and synthesis of Digital Signal Processing (DSP) algorithms and
architectures is to meet the throughput requirements of an application in a hardware …
architectures is to meet the throughput requirements of an application in a hardware …